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« Hardware task context switch on FPGA between heterogeneous reconfigurable devices in a cloud-FPGA environment ».

Author: A. Bourge
Advisor: F. Rousseau
Co-advisor: O. Muller
thesis reviewer(s): L. Lagadec, S. Pillement,
thesis examinator(s): O. Sentieys, M. Auguin,
These de Doctorat Université Grenoble Alpes
Speciality: Architecture des systèmes
Defense: November 23 2016
ISBN: 978-2-11-129219-2

Abstract

Current informatics greatly rely on hardware accelerators. Their mission is to accelerate domain-specific computation often too complex for a general purpose processor. A certain family of electronic devices, as known as reconfigurables, has been considered for accelerating computation in some cases: low volume production, need for recurrent updates, flexible use cases etc. However, they are still not being used enough compared with the benefits they offer. In order to facilitate a wider adoption, we propose to give more flexibility when using this kind of technology. This thesis presents and studies the capacity of reconfigurable resources to be shared. In order to do that, one should be able to switch between tasks executing on the resource. This technique is called context-switch, and has been in the literature for quite some time. In this work we propose to use a high-level synthesis flow in conjunction with this scheme. Thanks to the high-level synthesis flow, context-switchable circuit construction is automated. The produced circuits are portable because generically built. In addition, we add two steps in the high-level flow in order to give better characteristics to the final circuits. One checkpoint selection limits the states where context-switch is allowed. Moreover, an embedded mechanism is built. Thanks to these two steps, the produced circuits overheads and performances are better than circuits with naive mechanisms. A demonstration platform using FPGAs from different vendors is presented. It allows to test functionally and qualitatively the produced circuit used within a complex system.

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