PhD Thesis

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« Robustness analysis of digital integrated systems ».

Author: K. Chibani
Advisor: R. Leveugle
Co-advisor: M. Portolan
President of jury: J.-M. Portal
thesis reviewer(s): M. Sonza-Reorda, G. Di Natale,
thesis examinator(s): F. Miller,
These de Doctorat Université Grenoble Alpes
Speciality: Nanoélectronique et Nanotechnologies
Defense: November 10 2016
ISBN: 978-2-11-129-217-8


Integrated circuits are not immune to natural or malicious interferences that may cause transient faults which lead to errors (soft errors) and potentially to wrong behavior. This must be mastered particularly in the case of critical systems which impose safety and/or security constraints. To optimize protection strategies of such systems, it is essential to identify the most critical elements. The assessment of the criticality of each block allows limiting the protection to the most sensitive blocks. This thesis aims at proposing approaches in order to analyze, early in the design flow, the robustness of a digital system. The key criterion used is the lifetime of data stored in the registers for a given application. In the case of microprocessor-based systems, an analytical approach has been developed and validated on a SparcV8 microprocessor (LEON3). This approach is based on a new methodology to refine assessments of registers criticality. Then a more generic and complementary approach was implemented to compute the criticality of all flip-flops from a synthesizable description. The tool implementing this approach was tested on significant systems such as hardware crypto accelerators and a hardware/software system based on the LEON3 processor. Fault injection campaigns have validated the two approaches proposed in this thesis. In addition, these approaches are characterized by their generality, their efficiency in terms of accuracy and speed and a low-cost implementation. Another benefit is also their ability to re-use the functional verification environments.

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