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PhD Thesis


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« Development of test and diagnosis techniques for hierarchical mesh-based FPGAs ».

Author: Saif-Ur Rehman
Advisor: L. Anghel
Co-advisor: M. Benabdenbi
thesis reviewer(s): Fr. Pecheux, G. Di Natale,
thesis examinator(s): P. Prinetto,
These de Doctorat Université de Grenoble
Speciality: Nanoélectronique et Nanotechnologies
Defense: November 06 2015
ISBN: 978-2-11-129204-8

Abstract

FPGAs are used in complex digital systems mainly due to their reconfigurability and shorter time-to-market. Maintaining high reliability of such systems in advanced technology nodes requires FPGAs to be highly robust as well as efficient in detecting faults if occur during life time of the chip. Therefore, FPGAs are aimed to be tested exhaustively for defects, making FPGA testing a challenging task. Efficient testing techniques require to perform FPGA test in all its modes of operation in least possible time. Among major DFT approaches, Built-In Self-Test (BIST) is considered as the most efficient technique for FPGA testing as it exploits very well the FPGA reconfigurability and its regular structure. FPGA cluster size as well as interconnect topologies exploration is an ongoing optimization process as it severely impacts the routability, area saving and testability of the FPGA. Multilevel interconnect in mesh of clusters FPGA is a novel approach that promises to give better routability and area saving compared to classical mesh FPGAs. Although, BIST is a generic technique, test configurations are architecture specific. Most of the existing BIST solutions target specific commercial FPGAs using their dedicated CAD tools, making it difficult to apply such solutions on a new FPGA architecture. In this thesis, we provide BIST schemes for a complete test and diagnosis of logic and interconnect resources in a novel hierarchical mesh FPGA. The proposed technique ensures full test and diagnosis by performing selection of test paths. It uses only 2x2 adjacent logic resources. Using this scheme, any NxN FPGA array can be further tested by N parallel 2x2 array procedure which ultimately reduces the test time. Another strategy for test time reduction based on joint testing of logic and intra-cluster interconnect is also proposed. In addition to this, a thorough analysis of the cluster size impact on the testability of given FPGA is performed. Moreover, BIST schemes are developed for the FPGA clusters enriched with different defect-tolerant techniques. BIST simulation results are produced for various cluster sizes as well as for different defect-tolerant FPGAs. Automated tools are developed to generate test configuration bitstreams and to integrate them into a standard FPGA CAD flow. Experimental results show that 100% test coverage for stuck-at and pair-wise bridging faults can be achieved with a multiplexer or even gate-level diagnostic resolution.

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