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PhD Thesis


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« Design of a Network on chip (NoC) that tolerates multiple static and dynamic faults ».

Author: Yi Gang
Advisor: L. Anghel
Co-advisor: M. Benabdenbi
thesis reviewer(s): H. Mehrez, I. O'Connor,
These de Doctorat Université de Grenoble
Speciality: Micro et Nano Electronique
Defense: November 05 2015
ISBN: 978-2-11-129203-1

Abstract

A fast on chip communication fabric is vital to a multiprocessor system on chip (MPSoC). Network on chip becomes a most promising interconnection solution to replace the traditional shared BUS because of its higher performance in terms of throughput and scalability. Meanwhile, as the semiconductor technology scaling down and the number of devices integrated increases, the performance of circuits become more and more susceptible to various factors (manufacturing defects, process variation, wear-out, environmental constraints and so on). Facing the increasing probability of failure, the capacity of fault tolerance becomes mandatory in such NoC based MPSoCs, MPSoCs which may include in the future thousands of cores. In this thesis, a fault tolerant adaptive routing algorithm has been proposed, which can cope with transient, intermittent and permanent faults. Combined with some existing techniques, like flit retransmission and packet fragmentation, this approach allows tolerating numerous static and dynamic faults. Moreover, the use of a new congestion metric named “Flit Remain” helps decreasing the average latency in the case of heavy traffic.

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