PhD Thesis

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« Dedicated circuits to aging mechanisms study in avanced CMOS technology nodes: Design and measurements ».

Author: M. Saliva
Advisor: A. Bravaix
Co-advisor: L. Anghel
President of jury: M. Nicolaidis
thesis reviewer(s): F. Marc, B. Grandidier,
thesis examinator(s): V. Huard, F. Cacho,
These de Doctorat Université de Grenoble
Speciality: Micro et Nano Electronique
Defense: October 02 2015
ISBN: 978-2-11-129201-7


In the circuit development, specific attention must be paid to the MOS device reliability as a building block as well as a prototype reference circuit (CMOS) during the technology development. At device level, the different degradation mechanisms are characterized. In the final prototype, the product is characterized in accelerated aging conditions, but only the macroscopic parameters can be extracted. One objective of this thesis has been to link the circuit or system reliability and its building blocks. Also, the second important point has consisted in the development of 'smart' test solutions to improve testability and gain up structures so as to highlight the circuits aging monitoring and degradation compensation. Another family of ‘smart’ solutions has involved reproducing directly in the structure the excitement or the actual configuration as it is seen by elementary circuits or devices during their usage life (lab in situ). This work has been done in STMicroelectronics and has been developed over five chapters in order to integrate reliability progressively from devices to digital circuits: in the first chapter we are interested in technological developments that have been necessary from standard CMOS technologies (40LP, 28LP) to FDSOI technology for 28nm node as well as monotonic degradation mechanisms such as BTI and HCI. In the second chapter, we discuss the degradation mechanism of gate oxide breakdown (TDDB) that can be soft or hard in MOS transistors, we also deal with their physics mechanism, their localization; and a compact model has been developed. The third chapter focuses on the impact of BTI and HCI degradation mechanisms in dedicated circuits such as ring oscillators (RO), buffers and data paths under different AC/DC and activity conditions at high and ambient temperature in both 28nm LP and FDSOI technology nodes. Then, the fourth chapter tackles the gate oxide breakdown in ROs matrix and circuits composed of logic gates (ISCAS 432) in which soft breakdown apparition and impact are studied. Finally, the in-situ monitors are introduced and then applied to the circuit reliability, considering the results obtained in previous chapters of aging induced by BTI, HCI and TDDB.

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