PhD Thesis

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« A digitalization method adapted to an event-driven logic for ultra-low power purpose: Application to physiological signal pattern recognition ».

Author: T. Le Pelleter
Advisor: L. Fesquet
Co-advisor: A. Bonvilain
President of jury: P. Nouet
thesis reviewer(s): Y. Leduc, N. Noury,
These de Doctorat Université de Grenoble
Speciality: Micro et Nano Electronique
Defense: May 13 2015
ISBN: 978-2-11-129198-0


Our everyday life is highly dependent on mobile embedded systems. In order to make them suitable to different applications, they have undergone size reduction and lifetime extension. However, these improvements are currently limited by the possibilities of the integrated circuits technologies. In order to push back the boundaries, it is necessary to reconsider the whole digital signal processing chain from scratch to sustain the power consumption reduction in this kind of system. This work develops on the first hand a strategy that smartly uses the level-crossing sampling scheme and on the other combines this sampling method with event-logic to highly reduce the power consumption in mobile embedded systems. A digitalization method adapted to the recognition of physiological patterns application is described. A first event-logic (asynchronous) prototype implemented on FPGA proved the potential benefits that an adapted sampling scheme could offers to reduce activity compared to a uniform sampling scheme. Electrical simulations performed on a second prototype, also designed in asynchronous logic, with CMOS AMS 0.35 µm technology, validated a high gain in power consumption.

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