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« Contributions to Dynamic Binary Translation: instruction parallelism support and optimized translators generator ».

Author: L. Michel
Advisor: F. Pétrot
Co-advisor: N. Fournel
thesis reviewer(s): B. Goossens, E. Rohou ,
thesis examinator(s): F. Maraninchi , P. Feautrier,
These de Doctorat Université de Grenoble
Speciality: Nanoélectronique et Nanotechnologies
Defense: December 18 2014
ISBN: 978-2-11-129197-3

Abstract

Computing units embedded into modern integrated systems are com- plex, heterogeneous and numerous. Simulation widely used during both software and hardware design of these systems is becoming a real challenge. The simulator performance is mainly driven by the processors instruction set simulation approach, among which Dynamic Binary Translation (DBT) is one of the most promising technique. DBT aims at transla- ting on the fly instructions of the simulated processor (the target) into instructions that can be understood by the computer running the simulation (the host). This technique is fast, but designing a simulator based on it is complex. Indeed, the number of target architectures is limited, and furthermore, implementing a simulator is a complicated process because of long and error prone development. This PhD contributes to solve two major issues. The first contribution tackles the problem of supporting Very Long Instruction Word (VLIW) architectures as simulation targets, by studying their architecture peculiarities with regards to DBT. Some of these specificities, like explicit instruction parallelism make the translation to scalar hosts nontrivial. The solutions we propose bring simulation speed gains of two orders of magnitude compared to interpreter based simulators. The second contribution addresses the problem of automatic generation of DBT based simulators. With both target and host architectural descriptions, we produce a simulator optimised for this pair. This optimisation is done with an instructions matching process that finds host instruction candidates to simulate a target instruction. Although being experimental, our generator gives very promising results. It is able to produce a simulator for the MIPS architecture whose performances are close to a hand written implementation.

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