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PhD Thesis


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« Static analysis of configuration error effects in SRAM-based FPGAs and robustness improvement ».

Author: J.B. Ferron
Advisor: R. Leveugle
Co-advisor: L. Anghel
President of jury: F. Rousseau
thesis reviewer(s): H. Mehrez, F. Monteiro,
These de Doctorat Université de Grenoble
Speciality: Electronique, électrotechnique, automatique
Defense: March 26 2012
ISBN: 978-2-84813-186-3

Abstract

This thesis deals primarily with the analysis of the functional effects of errors in the configuration of SRAM-based FPGAs. These errors can be due either to natural perturbations (radiations, particles) or to malicious attacks, for example with a laser. The Xilinx Virtex II family is used as first case study, then a comparison is made with the ATMEL AT40K family. This work allowed us a better understanding of the real impact of perturbations, and of the error patterns that need to be taken into account when improving the robustness of a circuit implemented on this type of technology. This study required the development of specific design tools to automate the analyses. An innovative methodology is proposed for the evaluation of the configuration memory sensitivity to SEUs: a classification of configuration bits is made with respect to the effects produced on the application by a single bit-flip. This enables us to identify the most critical areas, and to propose selective hardening solutions, improving the global reliability of the application at low cost.

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