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PhD Thesis


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« Low-Cost Highly-Efficient Fault Tolerant Processor Design for Mitigating the Reliability Issues in Nanometric Technologies ».

Author: H. Yu
Advisor: M. Nicolaidis
Co-advisor: L. Anghel
President of jury: A. Dandache
thesis reviewer(s): A. Dandache, M. Sonza-Reorda,
These de Doctorat Université de Grenoble
Speciality: Micro et Nano Electronique
Defense: December 02 2011
ISBN: 978-2-84813-178-8

Abstract

Various applications of electronic systems, such as medical implant devices, or cryptographic chips for potable devices require both lower power dissipation and higher level of reliability. Moreover, as silicon-based CMOS technologies are fast approaching their ultimate limits, these requirements become necessary for the entire microelectronics industry. Indeed, by approaching these limits, power dissipation, fabrication yield, and reliability worsen steadily making further nanometric scaling increasingly difficult. Thus, before reaching these limits, these problems could become show-stoppers unless new techniques are introduced to maintain acceptable levels of power dissipation, fabrication yield and reliability. This thesis aims to develop a fault tolerant architecture for logic designs that conciliates the above contradictory challenges and provides a global solution to the yield, reliability and power dissipation issues in current and future nanometric technologies. The proposed fault tolerant architecture is expected to improve the fabrication yield and reliability while reducing the power dissipation of electronic components. It leads a breakthrough, since traditional fault-tolerant architectures introduce significant area and power penalties.

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