PhD Thesis

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« Study of methods and mechanisms for software-seamless data accesses in a multiprocessor system-on-chip ».

Author: P. Guironnet de Massas
Advisor: F. Pétrot
President of jury: J.-F. Méhaut
thesis reviewer(s): A. Greiner, O. Temam ,
These de Doctorat Grenoble INP
Speciality: Informatique
Defense: November 12 2009
ISBN: 978-2-84813-145-0


In order to provide evermore computational power, architects integrates dozen of processors in the same chip. The main goal of our work is to enhance data accesses using software-seamless solutions. Our context targets NoC based muliprocessor systems which contains L1 caches and distributed shared memory. In a first part, we show that the constraints evolution in embedded systems makes possible the usage of a write-through invalidate coherence protocol in such systems. We present also a novel method to evaluate and compare memory coherence protocols. In the second part we present a novel solution for on-chip data migration. It is hardware driven, and it dynamically and wisely places the data in order to decrease the mean cost access to memory.

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