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PhD Thesis


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« Reconfigurable, high throughput and low power VLSI architecture for advanced OFDM digital processing ».

Author: C. Sahnine
Advisor: F. Pétrot
Co-advisor: N.- E. Zergainoh
President of jury: M. Béllanger
thesis reviewer(s): E. Casseau, J.-F. Hélard,
These de Doctorat Institut National Polytechnique de Grenoble - INPG
Speciality: Micro et Nano Electronique
Defense: January 30 2009
ISBN: 978-2-84813-130-6

Abstract

Most current wireless LANs and future Beyond 3G and 4G mobile networks involve the multicarrier OFDM transmission, based itself on the digital processing of the fast Fourier transform. These systems should cover bandwidths in the order of several tens or even hundreds of MHz. The aim of this thesis was to study the architectures of integrated circuit for a high speed and multi-standard OFDM digital processing. These architectures require both higher speed processing to meet the required throughput, and reconfiguration for multi-standard applications. Moreover, these architectures should meet the requirement of reduced power consumption due to the embedded environment of mobile terminals. In terms of advanced solutions, one considers two different OFDM modulation patterns, the OFDM/ QAM and OFDM/OQAM. This latter requires a pulse shaping polyphase filter implemented in our study on the IOTA prototype function. One considers also SISO/MIMO functionalities. A comparative analysis of various FFT algorithms and architectures has led to identify the best approach which gives a good algorithm architecture adequation. This solution also incorporates the pulse shaping filter, more precisely implementing the IOTA function. One has therefore proposed a memory-based architecture using a time multiplexed operations on a coarse grained matrix optimized for the treatment of the FFT and of the pulse shaping filtering. This time approach allows a realization of advanced OFDM modulation for values of the parameter N, the number of subcarrier, from 64 to 8192 and the parameter L, the truncation length for pulse shaping filter, equal to 2, 4 and 8. The architecture of the matrix applies the same treatment on two or four streams of different samples, for modes MIMO 2x2 and 4x4 respectively. A strategy to manage memories has also been proposed. It is based on a memory banks approach to obtain various memory sizes and to enable the turn of the unnecessary memories. A first FPGA prototyping and an ASIC layout design have validated the functioning and the feasibility of the architecture. The FPGA prototyping platform used was the ML402 from Xilinx incorporating the FPGA XC4VSX35 from the Virtex-4 family. The ASIC layout design has been done using the submicronic 65 nm CMOS technology from STMicroelectronics. The performances obtained out of this architecture makes it a good candidate to cover the different standards based on OFDM modulation.

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