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« Transistor Level Automatic Generation of Radiation-Hardened Circuits ».

Author: C. Lazzari
Advisor: L. Anghel
Co-advisor: R. Reis
President of jury: R. Velazco
thesis reviewer(s): P. Fouillat, M. Sonza-Reorda,
These de Doctorat Grenoble INP
Speciality: Micro et Nano Electronique
Defense: December 07 2007
ISBN: 978-2-84813-113-9

Abstract

Deep submicron technologies have increased the challenges in circuit designs due to geometry shrinking, power supply reduction, frequency increasing and high logic density. One of the goals of this thesis is to develop EDA tools able to cope with these DSM challenges. This thesis is divided in two major contributions. The first contribution is related to the development of a new methodology able to generate optimized circuits in respect to timing and power consumption. A new design flow is proposed in which the circuit is optimized at transistor level. The second contribution of this thesis is related with the development of techniques for radiation-hardened circuits. The Code Word State Preserving technique is used to apply timing redundancy into latches and flipflops. Further, a new transistor sizing methodology for Single Event Transient attenuation is proposed. The sizing method is based on an analytic model. The model considers independently pull-up and pull-down blocks.

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