PhD Thesis

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« Software performance estimation in MPSoC design ».

Author: M. Oyamada
Advisor: A.-A. Jerraya
Co-advisor: F.R. Wagner
President of jury: F. Maraninchi
thesis reviewer(s): I. O'Connor, G.C.S. Araujo,
These de Doctorat Grenoble INP
Speciality: Micro et Nano Electronique
Defense: December 05 2007
ISBN: 978-2-84813-112-2


Nowadays, embedded system complexity requires new design methodologies. System-level methodologies are proposed to cope with this complexity, starting the design above the register-transfer level. Performance estimation tools are an important piece of system-level design methodologies, since they are used to aid design space exploration at an early design stage. The goal of this thesis is to define an integrated methodology for software performance estimation. Currently, embedded software usage is increasing, becoming multiprocessor system-on-chip a common solution to cope with flexibility, performance, and power requirements. The development of accurate software performance estimators is not trivial, due to the increased complexity of embedded processors. To drive processor selection at specification level, a novel analytic software performance estimator based on neural networks is proposed. The neural network enables a fast estimation at an early design stage. To target the software performance analysis at bus functional level, where mapping of the hardware and software components is already established, we use a global simulation model supporting performance profiling. The proposed software performance estimation methodology is linked to a hardware and software interface refinement environment named ROSES. The proposed methodology is evaluated through a case study of a multiprocessor MPEG4 encoder.

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