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PhD Thesis


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« Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS ».

Author: S. Bonacini
Advisor: R. Velazco
Co-advisor: K. Kloukinas
President of jury: R. Leveugle
thesis reviewer(s): L. Dusseau, S. Centro,
These de Doctorat Grenoble INP
Speciality: Micro et Nano Electronique
Defense: November 16 2007
ISBN: 978-2-84813-111-5

Abstract

The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Most of the microelectronics components developed for the first generation of LHC experiments have been designed with very precise experiment-specific goals and are hardly adaptable to other applications. Commercial On-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust programmable components for application in High Energy Physics (HEP) experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 μm CMOS technology. The FPGA under development is instead a 32 × 32 logic block array, equivalent to ~25k gates, in 0.13 μm CMOS. This work focussed also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design.

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