PhD Thesis

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« Contribution to the Synthesis of Quasi Delay Insensitive Asynchronous Circuits, Application to Secured Systems. ».

Author: B. Folco
Advisor: M. Renaudin
Co-advisor: G. Sicard
President of jury: R. Leveugle
thesis reviewer(s): Ch. Piguet, B. Rouzeyre,
These de Doctorat Grenoble INP
Speciality: Micro et Nano Electronique
Defense: October 04 2007
ISBN: 978-2-84813-108-5


The work presented in this thesis deals with the development of a design methodology for Quasi Delay Insensitive (QDI) circuits and its application to secured circuits. Contrary to synchronous circuits, asynchronous circuits are characterized by the absence of a global clock signal. These circuits are sequenced by a local mechanism of communication and synchronization. In addition to many properties of the asynchronous circuits such as the robustness, low consumption, low noise and excellent modularity, the properties of the QDI logic appear also particularly interesting to protect integrated circuits against attacks based on current analysis. However, the lack of methods and tools is a brake for their adoption in the industry. In this context, this thesis contributes to the development of a tool for the design of asynchronous circuits developed at TIMA laboratory called TAST.

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