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« CAT platform for mixed signal testing ».

Author: A. Bounceur
Advisor: S. Mir
Co-advisor: E. Simeu
These de Doctorat Institut National Polytechnique de Grenoble - INPG
Speciality: Micro et Nano Electronique
Defense: April 13 2007
ISBN: 978-2-84813-097-2

Abstract

The growing complexity of modern chips poses challenging test problems due to the requirement for specialized test equipment and the involved lengthy test times. This is particularly true for heterogeneous chips that comprise digital, analogue, and RF blocks onto the same substrate. Many research efforts are currently under way in the mixed-signal test domain. Theses efforts concern optimization of tests at the production stage (e.g. off-line) or during the lifetime of the chip (on-line test). A promising research direction is the integration of additional circuitry on-chip, aiming to facilitate the test application (Design For Test) and/or to perform Built-In-Self-Test. The efficiency of such test techniques, both in terms of test accuracy and test cost, must be assessed during the design stage. However, there is an alarming lack of CAT tools, which are necessary, in order to facilitate the study of these techniques and, thereby, expedite their transfer into a production setting. In this thesis, we develop a CAT platform that can be used for the validation of analogue test techniques. The platform includes tools for fault modeling, injection and simulation, as well as tools for analogue test vector generation and optimization. A new statistical method is proposed and integrated into the platform, in order to assess the quality of test techniques during the design stage. This method aims to set the limits of the considered test criteria. Then, the different test metrics (as Fault coverage, Defect level or Yield loss) are evaluated under the presence of parametric and catastrophic faults. Some specific tests can be added to improve the structural fault coverage. The CAT platform is integrated in the Cadence design framework environment.

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