PhD Thesis

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« Off-Line and On-Line BIST for Embedded Systems ».

Author: E. Simeu
Advisor: J.-M. Dion
HDR Université Joseph-Fourier - Grenoble I
Speciality: Micro et Nano Electronique
Defense: September 22 2005
ISBN: 2-84813-071-7


This report presents a summary of our research activities focusing on off-line testing and on-line supervision of embedded systems. Modern microelectronic manufacturing technologies and software tools make it feasible to integrate a complex system, into a single chip (SoC) able to hold all the components and functions that historically required a hardware board. Embedded systems made up of hardware and software generally contains a variety of integrated devices including digital, analogue, and even radio-frequency cores on the same chip. As these systems are gain sophistication, manufacturers are using them in increasingly critical applications that can result in injury, economic loss, or unacceptable inconvenience when they do not perform as required. This leads to new challenge for the test and for the real time supervision capabilities.The first part of this manuscript puts forward original BIST design methodology for analogue and mixed signal devices using embedded smart resources (embedded microprocessors and memories). The second part introduces different approaches for online supervision and discusses their applicability to online testing to of embedded ICs, including semiconcurrent and concurrent online testing strategies. It is attractive to adapt some of the results that are abundantly available in automatic control research to deal with the problem of online fault detection in electronic embedded systems. However, only some techniques are applicable to electronic systems because the design and implementation constrains are very different in both research fields. Compared to other known FDI architectures, it is shown that the model-based parity space approach is suitable for online testing of digital embedded systems with respect to electronic design constrains and allows not only for efficient fault coverage, but also for efficient implementation facilities.

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