PhD Thesis

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« Scheduling and optimizations for high-level synthesis of control designs ».

Author: M. Rahmouni
Advisor: A.-A. Jerraya
These de Doctorat Institut National Polytechnique de Grenoble - INPG
Defense: February 21 1997
Pages: 140


Most scheduling techniques in high-level synthesis are geared towards data flow dominated designs such as DSP applications. The goal of these algorithms is to optimize the data path cost. However, in modern control circuits, the performance of a design is dominated by the performance of the controller. Then, it is imperative to take into account the properties of such applications and develop techniques with the goal of optimizing the controller cost. This thesis presents new scheduling techniques for different controller architectures as well as a study on the interpretation of VHDL structures from a high-level synthesis point of view. The aim of the algorithms developed is to either reduce the controller area or to optimize the performance of the synthesized design. These algorithms have been implemented and integrated in the high-level synthesis tool AMICAL. Results show their efficiency when applied to real life control flow dominated circuits.