Research
AMfoRS
Architectures and Methods for Resilient Systems
since 2015
Research topics
- Multi-level specification and verification of hardware/software on-chip architectures: formal and semi-formal approaches
- System-level modeling, analysis and testing
- Dependability of integrated systems: fault detection/tolerance, on-line monitoring, self-adapting and self-healing circuits
- Dependability evaluations: fault injections and alternatives (analytical or formal approaches), prediction of ageing effects on lifetime
- Security of integrated systems: cryptographic accelerators, counter-measures against hardware attacks
The AMfoRS team targets crucial challenges regarding resilient integrated
systems. Our goal is twofold: guarantee that systems will not behave unexpectedly and ensure a substantial level of robustness and security. Our
work aims at increasing the synergies between verification technologies and
activities on the design and validation of reliable, safe and secure integrated
systems, with a focus on digital parts.
The expected outcomes of our research include methods, tools and hardware blocks necessary to justify trust in increasingly complex integrated systems and even cyber-physical systems.
The team takes part in several scientific challenges identified not only at the laboratory level, but also in the Research "poles" of University Grenoble-Alpes (especially the MSTIC pole) and more generally at the national level (French strategic directions) and international level (in particular European H2020 priorities).
The expected outcomes of our research include methods, tools and hardware blocks necessary to justify trust in increasingly complex integrated systems and even cyber-physical systems.
The team takes part in several scientific challenges identified not only at the laboratory level, but also in the Research "poles" of University Grenoble-Alpes (especially the MSTIC pole) and more generally at the national level (French strategic directions) and international level (in particular European H2020 priorities).
Last publications
Shah A., Cacho F., Anghel L., Aging Investigation of Digital Circuits using In-Situ Monitors, IEEE International Integrated Reliability Workshop (IIRW 2019), Stanford Sierra, Fallen Leaf Lake, UNITED STATES, 2019
Vatajelu I., Di Natale G., High-Entropy STT-MTJ-based TRNG, IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Ed. IEEE, Vol. , DOI: 10.1109/TVLSI.2018.2879439, 2019
Merandat M., Reynaud V., Valea E., Quévremont J., Maistri P., Leveugle R., Flottes M.-L., Dupuis S., Rouzeyre B., Di Natale G., A Comprehensive Approach to a Trusted Test Infrastructure, 4th International Verification and Security Workshop (IVSW 2019), Rhodes Island, GREECE, 2019
Valea E., Da Silva M., Di Natale G., Flottes M.-L., Rouzeyre B., A Survey on Security Threats and Countermeasures in IEEE Test Standards, IEEE Design & Test, Ed. IEEE, Vol. 36, No. 3, pp. 95-116, DOI: 10.1109/MDAT.2019.2899064, 2019
Vallero A., Savino A., Chatzidimitriou A., Kaliorakis M., Kooli M., Riera V., Di Natale G., Bosio A., Canal R., Gizopoulos D., Di Carlo S., Early System Reliability Analysis for Cross-layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems, IEEE Transactions on Computers, Ed. IEEE, Vol. 68, No. 5, pp. 765-783, DOI: 10.1109/TC.2018.2887225, 2019
