Research
AMfoRS
Architectures and Methods for Resilient Systems
since 2015
Research topics
- Multi-level specification and verification of hardware/software on-chip architectures: formal and semi-formal approaches
- System-level modeling, analysis and testing
- Dependability of integrated systems: fault detection/tolerance, on-line monitoring, self-adapting and self-healing circuits
- Dependability evaluations: fault injections and alternatives (analytical or formal approaches), prediction of ageing effects on lifetime
- Security of integrated systems: cryptographic accelerators, counter-measures against hardware attacks
The AMfoRS team targets crucial challenges regarding resilient integrated
systems. Our goal is twofold: guarantee that systems will not behave unexpectedly and ensure a substantial level of robustness and security. Our
work aims at increasing the synergies between verification technologies and
activities on the design and validation of reliable, safe and secure integrated
systems, with a focus on digital parts.
The expected outcomes of our research include methods, tools and hardware blocks necessary to justify trust in increasingly complex integrated systems and even cyber-physical systems.
The team takes part in several scientific challenges identified not only at the laboratory level, but also in the Research "poles" of University Grenoble-Alpes (especially the MSTIC pole) and more generally at the national level (French strategic directions) and international level (in particular European H2020 priorities).
The expected outcomes of our research include methods, tools and hardware blocks necessary to justify trust in increasingly complex integrated systems and even cyber-physical systems.
The team takes part in several scientific challenges identified not only at the laboratory level, but also in the Research "poles" of University Grenoble-Alpes (especially the MSTIC pole) and more generally at the national level (French strategic directions) and international level (in particular European H2020 priorities).
Team leader
MAISTRI PaoloLast publications
Fabero J.C., Mecha H., Franco F., Clemente J.A., Korkian G., Rey S., Cheymol B., Baylac M., Hubert G., Velazco R., Single Event Upsets Under 14-MeV Neutrons in a 28-nm SRAM-Based FPGA in Static Mode, IEEE Transactions on Nuclear Science, Ed. IEEE, Vol. 67, No. 7, pp. 1461-1469, DOI: 10.1109/TNS.2020.2977874, 2020
Skaf A., Ezzadeen M., Benabdenbi M., Fesquet L., Clocked and event-driven redundant adjustable precision computing, Microelectronics Reliability, Ed. Elsevier, Vol. 111, pp. 113729, DOI: 10.1016/j.microrel.2020.113729, 2020
Di Natale G., Bolchini C., Holding Conferences Online due to COVID-19: The DATE Experience, IEEE Design & Test, Ed. IEEE, Vol. 37, No. 3, pp. 116-118, DOI: 10.1109/MDAT.2020.2995140, 2020
Portolan M., Reynaud V., Maistri P., Leveugle R., Dynamic Authentication-Based Secure Access to Test Infrastructure, European Test Symposium (ETS 2020), Tallin, ESTONIA, 2020
Elshamy M., Di Natale G., Pavlidis A., Louërat M.-M., Stratigopoulos H., Hardware Trojan Attacks in Analog/Mixed-Signal ICs via the Test Access Mechanism, IEEE European Test Symposium (ETS 2020), Tallinn, ESTONIA, 2020
