Research
AMfoRS
Architectures and Methods for Resilient Systems
since 2015
Research topics
- Multi-level specification and verification of hardware/software on-chip architectures: formal and semi-formal approaches
- System-level modeling, analysis and testing
- Dependability of integrated systems: fault detection/tolerance, on-line monitoring, self-adapting and self-healing circuits
- Dependability evaluations: fault injections and alternatives (analytical or formal approaches), prediction of ageing effects on lifetime
- Security of integrated systems: cryptographic accelerators, counter-measures against hardware attacks
The AMfoRS team targets crucial challenges regarding resilient integrated
systems. Our goal is twofold: guarantee that systems will not behave unexpectedly and ensure a substantial level of robustness and security. Our
work aims at increasing the synergies between verification technologies and
activities on the design and validation of reliable, safe and secure integrated
systems, with a focus on digital parts.
The expected outcomes of our research include methods, tools and hardware blocks necessary to justify trust in increasingly complex integrated systems and even cyber-physical systems.
The team takes part in several scientific challenges identified not only at the laboratory level, but also in the Research "poles" of University Grenoble-Alpes (especially the MSTIC pole) and more generally at the national level (French strategic directions) and international level (in particular European H2020 priorities).
The expected outcomes of our research include methods, tools and hardware blocks necessary to justify trust in increasingly complex integrated systems and even cyber-physical systems.
The team takes part in several scientific challenges identified not only at the laboratory level, but also in the Research "poles" of University Grenoble-Alpes (especially the MSTIC pole) and more generally at the national level (French strategic directions) and international level (in particular European H2020 priorities).
Team leader
LEVEUGLE RégisLast publications
Plassan G., Conclusive formal verification of clock domain crossing properties, These de Doctorat, 2018
Mkhinini A., Maistri P., Leveugle R., Tourki R., Co-designed accelerator for homomorphic encryption applications, Advances in Science, Technology and Engineering Systems Journal (ASTESJ), Vol. 3, No. 1, pp. 426-433, DOI: 10.25046/aj030152, 2018
Alexandrescu D., Altun M., Anghel L., Ciriani V., Tahoori M., Bernasconi A., Logic synthesis and testing techniques for switching nano-crossbar arrays, Microprocessors and Microsystems, Ed. Elsevier, Vol. 54, pp. 14-25, DOI: 10.1016/j.micpro.2017.08.004, 2017
Plassan G., Peter H.J., Morin-Allory K., Sarwary S., Borrione D., Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings, VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability, revised selected contributions from 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Hollstein T., Raik J., Kostin S., Tšertov A., O'Connor I., Reis R (Eds.) , Ed. Springer , pp. 108-129, Vol. 508, DOI: 10.1007/978-3-319-67104-8, 2017
Benabdenbi M., Anghel L., Dimopoulos M., Gang Yi, Adaptive Routing for Fault Tolerance and Congestion Avoidance for 2D Mesh and Torus NoCs in Many-Core Systems-on-Chip, Advances in Microelectronics: Reviews, Sergei Y. Yurish (Eds.) , Ed. IFSA, International Frequency Sensor Association, pp. 405-435, Vol. 1, 2017
