Research
SLS
System Level Synthesis
since 1994
Research topics
- Parallel, configurable and reconfigurable architectures
- Software frameworks for integrated systems
- Synthesis, generation and simulation of digital integrated systems
The challenges that the micro/nanoelectronic system integration research is
currently facing is a huge increase of the number of processors in a chip. The
ITRS expects >1000 processing elements on a chip by 2020 for the consumer
market. In this context, there are very important issues to be solved:
To answer these questions, the activity of the System Level Synthesis Group focuses on the following themes:
- as the integration technology still progresses, can we define architectures which fully benefit from this trend, by exploiting at best the parallelism, parametrization and reconfiguration capabilities of these technologies?
- as we cannot expect the average programmer to be able to get the most performance out of these huge multiprocessor system, can we help him by providing innovative software frameworks to facilitate and optimize software integration?
- as the difficulties of HW/SW integration is unparalleled, can we provide synthesis, generation and simulation tools and methodologies to simplify, automate and verify system integration?
To answer these questions, the activity of the System Level Synthesis Group focuses on the following themes:
- Parallel, configurable and reconfigurable architectures
- Software frameworks for integrated systems
- Synthesis, generation and simulation of digital integrated systems
Team leader
MULLER OlivierLast publications
Perais A., Leveraging Targeted Value Prediction to Unlock New Hardware Strength Reduction Potential, IEEE/ACM International Symposium on Microarchitecture (MICRO 2021), Athens, GREECE, DOI: 10.1145/3466752.3480050, 2021
Trevisan Jost T., Compilation and optimizations for variable precision floating-Point arithmetic: from language and libraries to code generation, These de Doctorat, 2021
Faravelon A., Gruber O., Pétrot F., Removing Load/Store Helpers in Dynamic Binary Translation, Multi‐Processor System‐on‐Chip, Architectures, Liliana Andrade, Frédéric Rousseau (Eds.) , Ed. ISTE - International Scientific and Technical Encyclopedia, pp. 133-160, Vol. 1, DOI: 10.1002/9781119818298.ch7, 2021
Andrade Porras L.L., Rousseau F. (Eds.), Multi-Processor System-on-Chip 1: Architectures, Vol. 1, pp. 320, Ed. Wiley, Chichester, UK, 2021
Wicaksana A., Muller O., Rousseau F., Sasongko A., Maintaining Communication Consistency during Task Migrations in Heterogeneous Reconfigurable Devices, Multi-Processor System-on-Chip 1: Architectures, Liliana Andrade Porras & Frédéric Rousseau (Eds.) , Ed. Wiley, Chichester, UK, pp. 255-285, Vol. 1, 2021
