System Level Synthesis
since 1994

Research topics

photo SLS

The challenges that the micro/nanoelectronic system integration research is currently facing is a huge increase of the number of processors in a chip. The ITRS expects >1000 processing elements on a chip by 2020 for the consumer market. In this context, there are very important issues to be solved:
  • as the integration technology still progresses, can we define architectures which fully benefit from this trend, by exploiting at best the parallelism, parametrization and reconfiguration capabilities of these technologies?
  • as we cannot expect the average programmer to be able to get the most performance out of these huge multiprocessor system, can we help him by providing innovative software frameworks to facilitate and optimize software integration?
  • as the difficulties of HW/SW integration is unparalleled, can we provide synthesis, generation and simulation tools and methodologies to simplify, automate and verify system integration?

To answer these questions, the activity of the System Level Synthesis Group focuses on the following themes:
  • Parallel, configurable and reconfigurable architectures
  • Software frameworks for integrated systems
  • Synthesis, generation and simulation of digital integrated systems

Team leader

MULLER Olivier

Last publications

Bruant J., Horrein P.-H, Muller O., Groleat T., Pétrot F., (System)Verilog to Chisel Translation for Faster Hardware Design, 31th International Symposium on Rapid System Prototyping (RSP 2020), Virtual Conference, FRANCE, 2020
Fernandez-Mesa B.J., Andrade Porras L.-L., Pétrot F., Synchronization of Continuous Time and Discrete Events Simulation in SystemC, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Ed. IEEE, Vol. , DOI: 10.1109/TCAD.2020.3019204, 2020
Fernandez-Mesa B.J., Andrade Porras L.-L., Pétrot F., Accurate and Efficient Continuous Time and Discrete Events Simulation in SystemC, Design, Automation and Test in Europe (DATE 2020), Grenoble, FRANCE, 2020
Matoussi O., Pétrot F., Loop aware CFG matching strategy for accurate performance estimation in IR-level native simulation, Integration, the VLSI Journal, Ed. Elsevier, Vol. , 2019
Christodoulis G., Adapting a HPC runtime system to FPGAs, These de Doctorat, 2019
Annual activity report