System Level Synthesis
since 1994

Research topics

photo SLS

The challenges that the micro/nanoelectronic system integration research is currently facing is a huge increase of the number of processors in a chip. The ITRS expects >1000 processing elements on a chip by 2020 for the consumer market. In this context, there are very important issues to be solved:
  • as the integration technology still progresses, can we define architectures which fully benefit from this trend, by exploiting at best the parallelism, parametrization and reconfiguration capabilities of these technologies?
  • as we cannot expect the average programmer to be able to get the most performance out of these huge multiprocessor system, can we help him by providing innovative software frameworks to facilitate and optimize software integration?
  • as the difficulties of HW/SW integration is unparalleled, can we provide synthesis, generation and simulation tools and methodologies to simplify, automate and verify system integration?

To answer these questions, the activity of the System Level Synthesis Group focuses on the following themes:
  • Parallel, configurable and reconfigurable architectures
  • Software frameworks for integrated systems
  • Synthesis, generation and simulation of digital integrated systems

Team leader

MULLER Olivier

Last publications

Fernandez-Mesa B.J., Andrade Porras L.-L., Pétrot F., Simulation of Ideally Switched Circuits in SystemC, Asia and South Pacific Design Automation Conference (ASP-DAC 2021), Tokyo, JAPAN, DOI: 10.1145/3394885.3431417, 2021
Pierre L., Refinement rules for the automatic TLM-to-RTL conversion of temporal assertions, Integration, the VLSI Journal, Ed. Elsevier, Vol. 76, pp. 190-204, DOI: 10.1016/j.vlsi.2020.06.003, 2021
Christ M., Forget L., De Dinechin F., Lossless Differential Table Compression for Hardware Function Evaluation / Compression de table sans perte pour l'évaluation matérielle de fonctions, , Grenoble, FRANCE, 2020
Trevisan Jost T., Durand Y., Fabre Ch., Cohen A., Pétrot F., VP Float: First Class Treatment for Variable Precision Floating Point Arithmetic, International Conference on Parallel Architectures and Compilation Techniques (PACT 2020), pp. 355-356, Atlanta, UNITED STATES, 2020
Bruant J., Horrein P.-H, Muller O., Groleat T., Pétrot F., (System)Verilog to Chisel Translation for Faster Hardware Design, 31th International Symposium on Rapid System Prototyping (RSP 2020), Virtual Conference, FRANCE, 2020
Annual activity report