Research
SLS
System Level Synthesis
since 1994
Research topics
- Parallel, configurable and reconfigurable architectures
- Software frameworks for integrated systems
- Synthesis, generation and simulation of digital integrated systems
The challenges that the micro/nanoelectronic system integration research is
currently facing is a huge increase of the number of processors in a chip. The
ITRS expects >1000 processing elements on a chip by 2020 for the consumer
market. In this context, there are very important issues to be solved:
To answer these questions, the activity of the System Level Synthesis Group focuses on the following themes:
- as the integration technology still progresses, can we define architectures which fully benefit from this trend, by exploiting at best the parallelism, parametrization and reconfiguration capabilities of these technologies?
- as we cannot expect the average programmer to be able to get the most performance out of these huge multiprocessor system, can we help him by providing innovative software frameworks to facilitate and optimize software integration?
- as the difficulties of HW/SW integration is unparalleled, can we provide synthesis, generation and simulation tools and methodologies to simplify, automate and verify system integration?
To answer these questions, the activity of the System Level Synthesis Group focuses on the following themes:
- Parallel, configurable and reconfigurable architectures
- Software frameworks for integrated systems
- Synthesis, generation and simulation of digital integrated systems
Team leader
PETROT FredericLast publications
Prost-Boucle A., Bourge A., Pétrot F., High-Efficiency Convolutional Ternary Neural Networks with Custom Adder Trees and Weight Compression, ACM Transactions on Reconfigurable Technology and Systems (TRETS) , Ed. ACM IEEE, Vol. 31, No. 3, pp. Article No. 15, DOI: 10.1145/3270764, 2018
Matoussi O., Pétrot F., Loop aware CFG matching strategy for accurate performance estimation in IR-level native simulation, Integration, the VLSI Journal, Ed. Elsevier, Vol. , DOI: j.vlsi.2018.02.001, 2018
Chabot M., Requirement Driven automated tests for Cyber-physical Systems, These de Doctorat, 2018
Faravelon A., Acceleration of memory accesses in dynamic binary translation, These de Doctorat, 2018
France-Pillois M., Martin J., Rousseau F., Accurate MPSoC prototyping platform and methodology for the studying of the Linux synchronization barrier slowdown issues, International Symposium on Rapid System Prototyping (RSP'2018), pp. 56-62, Torino, ITALY, 2018
