5th IEEE International Workshop on
Test and Validation of High Speed Analog Circuits
Phoenix Convention Center, Phoenix, Arizona, USA
November 1-2, 2018
Held in conjunction with International Test Conference 2018
5th TVHSAC
Phoenix Convention Center, Phoenix, Arizona, USA
November 1-2, 2018

Workshop Overview

 

TVHSAC – Opening Keynote by Prof. A. Chatterjee from Georgia Tech

The IEEE Workshop on Test and Validation of High Speed Analog Circuits (TVHSAC) is a forum to address the pre-silicon and post-silicon validation, manufacturing test, in-field reliability and security challenges in AMS circuits and systems. This year, we have opening keynote given by Prof. A. Chatterjee from Georgia Tech on exiting topics on machine learning applications for post-silicon validation of mixed-signal circuits and systems. Please register soon at https://www.badgeguys.com/reg/2018/itc/register.aspx as the deadline for registration discount ends on Oct. 8 2018!


TVHSAC – Invited Talk by Srini Rajappa, Senior Director of Mixed Signal IP Solutions Group from Intel

The IEEE Workshop on Test and Validation of High Speed Analog Circuits (TVHSAC) is a forum to address the pre-silicon and post-silicon validation, manufacturing test, in-field reliability and security challenges in AMS circuits and systems. This year, we have an interesting invited talk given by Srini Rajappa, Senior Director of Mixed Signal IP Solutions Group from Intel on current trends, challenges and opportunities in High-Speed Mixed-Signal PHY designs for a Data-Centric world. Please register soon at https://www.badgeguys.com/reg/2018/itc/register.aspx as the deadline for registration discount ends on Oct. 8 2018!


TVHSAC – Invited talk by Prof. B. Floyd from North Carolina State University

The IEEE Workshop on Test and Validation of High Speed Analog Circuits (TVHSAC) is a forum to address the pre-silicon and post-silicon validation, manufacturing test, in-field reliability and security challenges in AMS circuits and systems. This year, we have an interesting given by Prof. B. Floyd on code-modulated embedded test and calibration of phased arrays. Please register soon at https://www.badgeguys.com/reg/2018/itc/register.aspx as the deadline for registration discount ends on Oct. 8 2018!


Today, we are in the internet-of-things (IoT) era - an era of sensors and components connected across a high speed communication infrastructure with analysis by massive data center “clouds”, the building blocks are systems-on-chip (SoC) integrated with several diverse IP modules. Analog and mixed-signal (AMS) circuits form many of the critical components of SoCs that push the boundaries of high bandwidth and low power. AMS circuits, such as phase-locked loops, sensors, amplifiers, wired and wireless interfaces are often embedded in a chip with limited controllability to access them.

The demand for high performance, high bandwidth and low power has resulted in AMS designs operating at their margins. The unimaginable levels of integration has come at the cost of increased manufacturing process variations, vulnerability to defects, and accelerated device aging. In this scenario, verifying and validating AMS circuits, which are particularly sensitive to variations and electrical noise, in both pre-silicon and post-silicon phases, has become a great challenge. Effective diagnosis to improve AMS yield, and manufacturing test methods to detect catastrophic faults and unexpected process excursions that have contributed to increased AMS-related customer returns are a necessity. Further, sensitive AMS circuits such as those used in health and automotive products need to have a high degree of in-field reliability requiring fault tolerance and adaptive operation. Since most AMS circuits are often the gateways to a SoC, ensuring their secure design is of vital importance to prevent compromising the security of the chip. These quality objectives should be met under market requirements of aggressively low product cost and product cycle time.

The IEEE Workshop on Test and Validation of High Speed Analog Circuits (TVHSAC) is a forum to address the pre-silicon and post-silicon validation, manufacturing test, in-field reliability and security challenges in AMS circuits and systems.

The areas of interest include (but not limited to):

  • Built-in test and design-for-test
  • Self-healing, self-calibration and self-adaptation techniques
  • Sample selection for pre-silicon and post-silicon validation
  • Behavioral modeling
  • Efficient mixed-signal simulation
  • Analog fault modeling and fault simulation
  • Analog and mixed-signal diagnosis
  • Reliable and secure AMS circuit design
  • Test access mechanism
  • Analog test bus design
  • SERDES test and characterization
  • RF circuits test and characterization
  • High speed data converter test and characterization
  • High speed PLL test and characterization
  • Precision delay-line test and characterization
  • Clock jitter and skew measurement
  • Phase noise measurement
  • AC and DC supply noise measurement
  • ATE technology
  • Board technology
  • Economics of test and yield optimization