10th IEEE International On-Line Testing Symposium
Tivoli Ocean Park Hotel, Funchal, Madeira Island, Portugal
July 12-14, 2004

Technical Program
Monday July 12th, 2004
07.30 - 08.30 Registration
08.30 - 08.45 Welcome Message
General Co-Chairs: M. Nicolaidis, J.P. Teixeira
Program Co-Chairs: R. Leveugle, C. Metra
08.45 - 9.30 Keynote Session
Moderator: Y.Zorian, Virage Logic (USA)
A Pragmatic Approach to On-Line Testing,
V. Agarwal, LogicVision (USA)
09.30 - 09.45    
9.45 - 10.45 Session 1: Timing and Transient Faults
Moderator: J. Abraham, University of Texas at Austin (USA
1.1. Modeling and Simulation of Time Domain Faults in Digital Systems,
D.B. Júnior, F. Vargas, M.B. Santos, I. Teixeira, J.P. Teixeira, PUCRS Porto Alegre, IST/INESC-ID Lisboa
1.2. Sizing CMOS Circuits for Increased Transient Fault Tolerance,
Y.S. Dhillon, A.U. Diril, A. Chatterjee, A.D. Singh, Georgia Institute of Technology, Auburn University
1.3. Low-Area and Fast On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop,
J.M. Cazeaux, M. Omaña, C. Metra, University of Bologna
10.45 - 11.00    
11.00 - 12.00 Session 2: Self Testing and Self Checking Circuits
Moderator: R. Stefanelli, Politecnico di Milano (Italy)
2.1. Necessary and Sufficient Conditions for the Existence of Totally Self-Checking Circuits,
V. Saposhnikov, Vl. Saposhnikov, A. Morozov, M. Gössel, Petersburg State Transport University, University of Potsdam
2.2. Self-Checking Code-Disjoint Carry-Select Adder with Low Area Overhead by Use of Add1-Circuits,
V. Ocheretnij, D. Marienfeld, E.S. Sogomonyan, M. Gössel, University of Potsdam
2.3. A Hierarchical Self Test Scheme for SoCs,
C. Kretzschmar, C. Galke, H.T. Vierhaus, Brandenburg University of Technology Cottbus
12.00 - 14.00 Lunch
14.00 - 15.00 Session 3: Checker and Voter Design
Moderator: Y. Savaria, Ecole Polytechnique de Montréal (Canada)
3.1. Single-Output Embedded Checkers for Systematic Unordered Codes,
S. Tarnick, 4TECH GmbH
3.2. A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations,
A. Rao, T. Haniotakis, Y. Tsiatouhas, V. Kaky, Southern Illinois University, University of Ioannina
3.3. New High-Speed CMOS Self-Checking Voter,
J.M. Cazeaux, D. Rossi, C. Metra, University of Bologna
15.00 - 15.15    
15.15 - 16.15 Session 4: Concurrent Error Detection
Moderator: M. Abadir, Motorola (USA)
4.1. Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory Blocks,
A. Krasniewski, Warsaw University of Technology
4.2. Low Cost On-line Testing of RF circuits,
M. Negreiros, L. Carro, A.A. Susin, Universidade Federal do Rio Grande do Sul
4.3. Hybrid Soft Error Detection by Means of Infrastructure IP cores,
L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante, Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS), Politecnico di Torino
16.15 - 16.30    
16.30 - 17.30 Panel Session
Organizer: Y. Zorian, Virage Logic (USA)
Title: "On Emerging Field Reliability and Dependability Challenges"
18.00 Welcome Dinner

Tuesday, July 13th, 2004
08.30 - 09.30 Session 5: Microprocessor On-Line Testing
Moderator: J. Hayes, University of Michigan (USA)
5.1. A Comparative Study of the Design of Synchronous and Asynchronous Self-Checking RISC Processors,
P.D. Hyde, G Russell, University of Newcastle upon Tyne
5.2. Testing of Hard Faults in Simultaneous Multithreaded Processors,
E.F. Weglarz, K.K. Saluja, T.M. Mak, University of Wisconsin, Intel Corporation Santa Clara (CA)
5.3. Fault Detection Enhancement in Cache Memories Using a High Performance Placement Algorithm,
H.R. Zarandi, S.G. Miremadi, H. Sarbazi-Azad, Sharif University of Technology
09.30 - 09.45    
09.45 - 10.45 Session 6: On-Line Testing Evaluation
Moderator: R. Velazco, TIMA (France)
6.1. Transient Faults Emulation of Circuits in Platform FPGAs,
M.G. Valderas, C.L. Ongil, M.P. Garcia, L. Entrena Arrontes, Universidad Carlos III de Madrid
6.2. On the Evaluation of SEU Sensitiveness in SRAM-based FPGAs,
P. Bernardi, M. Sonza Reorda, L. Sterpone, M. Violante, Politecnico di Torino
6.3. Asynchronous Circuits Sensitivity to Fault Injection,
Y. Monnet, M. Renaudin, R. Leveugle, TIMA laboratory
10.45 - 11.00    
11.00 - 12.00 Session 7: Error Correcting Code Based Fault Tolerance
Moderator: J. Karlsson, Chalmers University (USA)
7.1. Designing a High Speed Decoder for Cyclic Codes,
A. M'Sir, F. Monteiro, A. Dandache, B. Lepley, University of Metz
7.2. Impact of ECCs on Simultaneously Switching Outputs Noise for On-Chip Busses of High Reliability Systems,
D. Rossi, A. Muccio, A.K. Nieuwland, A. Katoch, C. Metra, University of Bologna, Philips Research Laboratories
7.3. A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities,
G.C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, A. Salsano, University of Rome "Tor Vergata"
12.00 - 14.00 Lunch
14.00 - 15.20 Session 8: Reconfiguration, Repair and Reuse for Fault Tolerance
Moderator: A. Salsano, University Roma II (Italy)
8.1. A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies,
A. Agarwal, B.C. Paul, H. Mahmoodi, A. Datta, K. Roy, Purdue University
8.2. Scrubbing Away Transients and Jiggling Around the Permanent: Long Survival of FPGA Systems Through Evolutionary Self-Repair,
M. Garvie, A. Thompson, University of Sussex
8.3. Hardware Reconfiguration Scheme for High Availability Systems,
C. Metra, A. Ferrari, M. Omaña, A. Pagni, University of Bologna, STMicroelectronics
8.4. Operating System Function Reuse to Achieve Low-cost Fault Tolerance,
M. Portolan, R. Leveugle, TIMA Laboratory
15.20 - 15.35    
15.35 - 16.35 Session 9: Posters
Moderator: S. Hellebrand, University of Innsbruck (Austria)
Coordinator: E. Dupont, iRoC technologies, France
9.1. A new Code for Continuous Automotive High Speed Data Exchange with reduced EMI and Partial Error Correction Possibilities,
E. Böhl, E. Dilger, Robert Bosch Company
9.2. A Matlab Based On-Chip Signal Generation and Analysis Environment for Mixed Signal Circuits,
T. O'Shea, I. Grout, University of Limerick
9.3. Automated Logic SER Analysis and On-Line SER reduction,
A.K. Nieuwland, P. Gindner, Philips Research Laboratories, University of Karlsruhe
9.4. On the Design of Long-life Reliable Systems for Ground-based Applications,
J.M. Vieira dos Santos, ISEP
9.5. On-line Monitoring Capabilities of Oscillation Test Techniques: Results Demonstration in an OTA,
R. Picos, M. Roca, E. Isern, S.A. Bota, E. Garcia, Universitat Illes Balears
9.6. An Intrinsically Robust Technique for Fault Tolerance under Multiple Upsets,
C.A.L. Lisbôa, L. Carro, Universidade Federal do Rio Grande do Sul
9.7. Survey of the Algorithms in the Column-matching BIST Method,
P. Fiser, H. Kubátová, Czech Technical University
9.8. A Partitioning Technique to Reduce Power and Test-Application Time in Test-Per-Scan BIST,
D. Ghosh, S. Bhunia, K. Roy, Purdue University
9.9. Optimization of the Theory of Fault Detection and Diagnosis for Alleviation of the State Explosion Problem and Development of CAD Tools for On-line Testing of Digital VLSI Circuits,
S. Biswas, S. Mukhopadhyay, A. Patra, Indian Institute of Technology
17.00 Social Event (Tour and Gala Dinner)

Wednesday, July 14th, 2004
08.30 - 09.30 Session 10: Built In Self Test
Moderator: H-J. Wunderlich, Stuttgart University (Germany)
10.1. BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs,
P. Girard, O. Héron, S. Pravossoudovitch, M. Renovell, Université de Montpellier II
10.2. Accumulator Based Test-per-Scan BIST,
P. Karpodinis, D. Kagaris, D. Nikolos, University of Patras, Southern Illinois University, Computer Technology Institute
10.3. A BIST-based Charge Analysis for Embedded Memories,
B. Alorda, V. Canals, I. de Paul, J. Segura, Universitat Illes Balears
09.30 - 09.45    
09.45 - 10.45 Session 11: Safety and Security
Moderator: D. Gizopoulos, University Pireus (Greece)
11.1. A System for Fault Detection and Reconfiguration of Hardware Based Active Networks,
N.G. Bartzoudis, A.G. Fragkiadakis, D.J. Parish, J.L. Núñez, Loughborough University
11.2. Fault Tolerant Mechatronics,
E. Dilger, R. Karrelmeyer, B. Straube, Robert Bosch GmbH, Fraunhofer-Institut für Integrierte Schaltungen
11.3. Scan Design and Secure Chip,
D. Hély, F. Bancel, M.L. Flottes, B. Rouzeyre, M. Renovell, N. Bérard, ST Microelectronics, LIRMM
10.45 - 11.00    
11.00 - 12.00 Session 12: Dependability Evaluation
Moderator: E. Simeu, TIMA (France)
12.1. On combining Fault Classification and Error Propagation Analysis in RT-level Dependability Evaluation,
A. Ammari, K. Hadjiat, R. Leveugle, TIMA Laboratory
12.2. Performance Evaluation and Failure Rate Prediction for the Soft Implemented Error Detection Technique,
B. Nicolescu, Y. Savaria, R. Velazco, Ecole Polytechnique de Montréal, TIMA Laboratory
12.3. Experimental Evaluation of Master/Checker Architecture Using Power Supply- and Software-Based Fault Injection,
A. Rajabzadeh, S.G. Miremadi, M.M. Dezfuly, Sharif University of Technology
12.00 - 14.00 Lunch
14.00 - 15.00 Panel Session
Organizer: R. Aitken, Artisan (USA)
Title: "Reliability Implications of Statistical Design"
15.00 Closing