The pervasiveness of electronic systems in modern societies raises drastically the requirements to protect them against intentional attacks affecting security.
Nanometric scaling and the related aggressive reduction of device geometries steadily worsens noise margins; process, voltage and temperature variations; aging and wear-out; soft error and EMI sensitivity; power density and heating; which are also worsening by the rapidly increasing complexity of modern SoCs. It is therefore mandatory mitigating these issues, for achieving acceptable levels of yield, reliability, and lifespan. Furthermore, these issues are making increasingly difficult meeting low power and high performance, which are paramount requirements in modern SoCs and numerous applications. Indeed:
- Extra circuitry used in fault mitigation architectures increases power;
- Supply voltage reduction (often used to reduce power), affects yield, reliability, and lifespan, as it reduces noise margins and increases therefore the sensitivity to soft-errors and EMI, and also increases circuit delays that increases the sensitivity to timing faults;
- Furthermore: Reducing supply voltage for reducing power affects performance as it increases circuit delays; Increasing clock frequency for increasing performance, affects yield, reliability, and lifespan, as it increases the sensitivity to timing faults and soft-errors, and it also affects power as it increases dynamic power and may also require increasing supply voltage for reducing circuit delays.
- Design for Timing is also further related with Design for Reliability, as in real time systems timing properties are as important as functional properties in delivering correct operation.
These trends have made mandatory the development of efficient Design for Robustness approaches for mitigating these pluralities of threats. However, as Robustness-related DfX techniques are proliferating (Design for Test, Design for Debug, Design for Yield, Design for Reliability, Design for Low-Power, Design for Timing Performance, Design for Security, Design for Verification…), and also as these techniques often weaken the goals of each other, it is often very difficult to guarantee that a design meets all its target specifications. Thus, it becomes mandatory to address all these techniques holistically in order to improve their global efficiency: achieve all the robustness requirements of each design, and moderate their cost. There is therefore a major need for a consolidated international forum bringing together specialists from all these domains to enhance interactions and cross-fertilization. The IEEE Federative Event on Design for Robustness (FEDfRo), was initiated to meet this goal by bringing together:
- IOLTS: International Symposium on On-Line Testing and Robust System Design
a well-established IEEE forum on Design for Quality, Design for Yield, Design for Reliability, and Low-Power design based on Design for Reliability approaches, mostly addressing digital systems;
- PATMOS: International Symposium on Power and Timing Modeling, Optimization and Simulation
a well-established IEEE forum on Power and Timing Modeling, Optimization and Simulation.
- IMSTW: the International Mixed-Signal Testing Workshop
a well-established IEEE forum addressing these techniques in the context of mixed-signal circuits
which starting from this year is becoming part of IOLTS (please click here for more information)
- IVSW: the International Verification and Security Workshop
a new IEEE forum started on 2016 and addressing all Verification and Security issues associated with electronic systems.
These events will be held in the same location and will run in parallel. To encourage interactions, anyone registered in any of them can freely attend sessions of the other three events. All social activities will also be done jointly to increase interaction and cross fertilization among attendees.