New Initiative

1st Federative Event on Design for Robustness (FEDfRo)

Hotel Eden Roc, Sant Feliu de Guixols, Catalunya, Spain
July 4-6, 2016

Nanometer scaling and the related aggressive reduction of device geometries steadily worsens noise margins; process, voltage and temperature variations; aging and wear-out; soft error and EMI sensitivity; power density and heating; and make mandatory the use of efficient techniques for improving yield and reliability, extending lifespan, and reducing power dissipation of modern SoCs. Additionally, the rapidly increasing complexity of modern SoCs further aggravates these issues, and makes it extremely difficult to guarantee that the design of these chips meet their specifications.

Furthermore, the pervasiveness of electronic systems in modern societies, and their ubiquitous implication in all aspects of our everyday lives, drastically raises the requirements to protect modern electronic systems against all these threats, as well as versus those induced by intentional attacks against their security.

These trends have made mandatory the development of efficient Design for Robustness approaches for mitigating these pluralities of threats. However, as DfX techniques are proliferating (Design for Test, Design for Debug, Design for Yield, Design for Reliability, Design for Low-Power, Design for Security, Design for Verification, …), it becomes mandatory to address these issues holistically, in order to moderate their impact on area, power, and/or performance, and increase their global efficiency. There is therefore a related need for an international consolidated forum bringing together specialists from all these domains to enhance interactions and cross-fertilization. The Federative Event on Design for Robustness (FEDfRo) was initiated to meet this goal, and was established by bringing together.

Keynote Plenary Session:
Driving opportunities and technical challenges of the next wave of semiconductors devices Karim Arabi, Vice President R&D at Qualcomm

v  IOLTS: the 22nd International On-Line Testing Symposium      
http://tima.univ-grenoble-alpes.fr/conferences/iolts/iolts16/,
a well-established IEEE forum on Design for Quality, Design for Yield, Design for Reliability, and Low-Power design based on Design for Reliability approaches, mostly addressing digital systems;

v  IMSTW: the 21st International Mixed-Signal Testing Workshop        
http://tima.univ-grenoble-alpes.fr/conferences/imstw/imstw16/,
a well-established IEEE forum addressing these techniques in the context of mixed-signal circuits;

v  IVSW: the 1st International Verification and Security Workshop      
http://tima.univ-grenoble-alpes.fr/conferences/ivsw/ivsw16/,
a new IEEE forum addressing all Verification and Security issues associated with electronic systems.

The above events are soliciting papers in their respective areas. Those events will be held in the same location and will run in parallel. To encourage interactions, anyone registered in one of the events can freely attend sessions of the other two events. All social activities will also be done jointly to increase interaction and cross fertilization among attendees.  


Coordinators

Publicity Chair

Michael Nicolaidis

TIMA Laboratory

Grenoble, France

Tel: +33 (0) 476 574696

michael.nicolaidis@imag.fr

Florence Azais

LIRMM

Montpellier, France

Tel: +33 (0) 467 418625

florence.azais@lirmm.fr

Magdy Abadir

Abadir and  Associates

Austin, Texas USA

Tel: +1 (512) 5762701

magdy.abadir@gmail.com

Stefano Di Carlo

Polotecnico di Torino

Torino, Italy

Tel: +39 (0) 115 647080

stefano.dicarlo@polito.it


For all updated information, please visit the event web site:  http://tima.univ-grenoble-alpes.fr/conferences/fedfro