2nd IEEE International On-Line Testing Workshop
Hotel Helianthal, Saint-Jean de-Luz, Biarritz, France - July 8-10, 1996
Monday, July 8, l996
7:00 - 8:30 Registration
8:30 - 8:50 Opening Address
8:50 - 9:50
- Session 1: Invited Talks: On-line Testing Practice
Moderator : B. Courtois, TIMA
- Haim Levendel - Lucent Tecnology : On-Line Testing and Diagnosis
of Telecommunication Systems
- Jack Stiffler - Sequoia Systems : On-Line Fault Tolerant Monitoring
9:50 - l0:20 Coffee Break
l0:20 - l2:00
- Session 2: Monitoring Reliability Relevant Parameters
Moderator : TBA
2.1 Thermal Monitoring of Self-Checking Systems, V. Szekely, M. Rencz, TU. of Budapest, J.M. Karam, M. Lubaszewski, B. Courtois, TIMA
2.2 Oscillation Built-in Self-Test of Mixed-Signal IC with Temperature and Current Monitoring, K.Arabi, B. Kaminska, Ecole Polytechnique de Montreal
2.3 An Approach to On-Line Differential Thermal Testing, J. Altet, A. Rubio, U. Politechnica de Catalunia
2.4 On a Highly Observable Static and Dynamic Signature for CMOS Circuit Testing, X. Champac, J. Figueras, A. Rubio, U. Politecnica de Catalunya
2.5 Built-in Current Sensors in Mixed Circuit Test Based on Dynamic Power Supply Current, N. Pelaez, R. Mozuelos, M. Martinez S. Bracho, U. of Cantabria
l2:00 - 13:30 Lunch
13:30 - 14:50
- Session 3: Techniques for Radiation Effects
Moderator : TBA
3.1 Fault Tolerant Operation of Artificial Neural Networks Exposed to Radiation, R. Velazco, P. Cheynet, A. Assoum, LSR/IMAG, R. Ecoffet, CNES
3.2 Design of Radiation Hardened Memories, T. Calin, M. Nicolaidis, TIMA, R. Velazco, LSR/IMAG
3.3 Clocked Dosimeter Compatible Digital CMOS, E. Moreno, B. Iniguez, M. Roca, J. Segura, E. Isern, UIB
3.4 On-Line Measurement Under High Gamma and Neutron Radiation: The Choice of Transducers and Signal Processing Electronics, M. Decreton, S. Coenen, SCK.CEN
14:50 - 15:20 Coffee Break
15:20 - 17:00
- Session 4: Fail-Safe and Self-Checking Designs
Moderator : A. Somani, U. of Washington
4.1 A Three Rail Totally Self Checking Error Indicator, N.Gaitanis, P. Kostarakis, A. Paschalis, DEMOCRITOS
4.2 Using FPGAs for the Implementation of Fail Safe Interfaces, H. Berviller, A. Dandache, F. Monteiro and B. Lepley, U. of Metz
4.3 Design of Self-Checking Unidirectional Combinational Circuits with Low Area Overhead, V. Saposhnikov, Vl. Saposhnikov, U. for Railway- Engineering, A. Morosov and, M. Gossel, U. of Potsdam
4.4 IFIS - An On-Line Testing Methodology Using Dual-Rail Data Coding, M. Saeed, J. Yeandel, D. Thulborn, S. Jones, Loughborough U. of Techno.
4.5 Power Dissipation Considerations when Implementing Fault Detection in FSMs, X. Wendling, R. Rochet, R. Leveugle, INPG
17:00 - 19:00
- Poster Session
P.1 Design and Implementation of a Reliable Fail-Safe Interface and Its Applications, M. Wong, W. Mak, Hong Kong Polytechnic U.
P.2 Functional Test Generation for On-Line Testing RISCs, S.Sharshunov, A. Koshevenko, Far Eastern State Technical U.
P.3 Hardware Fault-Tolerance Using Self Checking Modules, K. Kuchukyan, STaR Lab. American U. of Armenia
P.4 A Parallel Test Generation for Combinational Circuits Based on Boolean Satisfiability Technology, Y. Sun, D. Wei, Institute of Computing Technology, Academia Sinica
P.5 Fault Localization for On-Line Testable Designs Realised Using Dual-Rail Design Methodology, J. Yeandel, D. Thulborn, M. Saeed, S. Jones, Loughborough U. of Technology
P.6 Use of Embedded TSC Checkers for Error Detection and Error Correction, R. Latypov, Kazan State U.
P.7 A Built-In Self Test Structure for Pulse-Mode Digital Sequential Circuits, A. Chiari, Fondazione "Ugo Bordoni"
P.8 Implementation of Logic Controllers with Concurrent Fault Detection Capabilities in PLDs, J. Andina, S. Gomez, E. Mandado, U. de Vigo
P.9 Sequential Test Compaction for Test Embedding, F. Ferrandi, F. Fummi, R. Bevacqua, L. Guerrazzi, Politecnico di Milano
P.10 Built-in Laser Sensitive Cells for a New Testing Technique, H. Lapuyade, P. Fouillat, J. Dom, U. Bordeaux I
P.11 On the Testability of Low-Power Optimization Circuits, M. Perakis, H. Vergos, D. Nikolos, U. of Patras
P.12 Design and Synthesis of Self-Checking Implementations of Boolean Interpreted Petri Nets, B. Roussev, American U. in Bulgaria
P.13 Towards a General Test Presentation in the Test Sequencing Problem, A. Zuzek, A. Biasizzo, F. Novak, Jozef Stefan Institute
P.14 A Unified Error Detection Scheme for Operations Over Generalized Number System, N. Venkateswaran, B. Prakash, S. Karthik, S. Kailash, C. Raghavan, Sri Venkateswara College of Engineering
P.15 A Multiple-Level Connection Management Strategy for Survivable ATM Networks, S. Yahia, C. Robach, LGI-IMAG
P.16 On the Hierarchical Approach to the Problem of Fault-Tolerant and Performance Evaluation, S. Frenkel, Russian Academy of Sciences
Tuesday, July 9, l996
8:30 - 9:50
- Session 5: BIST
Moderator : A. Ivanov, UBC
5.1 Coupling Genetic ATPG and Synthesis of Pattern Generators for Deterministic BIST, F. Corno, P. Prinetto, M. Sonza Reorda, Politecnico di Torino
5.2 A Mixed-mode BIST Using Embedded Processors, S. Hellebrand, H.J. Wunderlich, A. Hertwig, U. of Siegen
5.3 A Bist Scheme for Non-Volatile Memories, P. Olivo, M. Dalpasso, U. of Ferrara
5.4 ILA BIST for FPGAs: A Free Lunch with Gourmet Food, M. Abramovici, Lucent Technologies, C. Stroud, U. of Kentucky
9:50 - 10:20 Coffee Break
10:20 - 12:00
- Session 6: Self-Checking Designs
Moderator : TBA
6.1 Concurrent Error Detection, in Arithmetic Operations, Using New Modified Berger Code, A. Maamar, G. Russell, U. of Newcastle
6.2 Self-Checking Sequential Circuits with Retiming, S. Lejmi, G. Bois, Y. Savaria, Ecole Polytechnique de Montreal
6.3 Efficient Fault-Secure Shifter Design, R. Duarte, M. Nicolaidis, TIMA, H. Bederr, Texas Instruments, Y. Zorian, Lucent Technologies
6.4 Synthesis of Self-Dual Multi-Output Combinational Circuits for On-Line Testing, V. Saposhnikov, Vl. Saposhnikov, U. for Railway-Engineering, V. Moshanin, M. Gossel, U. of Potsdam
6.5 Concurrent Delay Detection in Duplication Systems, A Paschalis, D. Gizopoulos, N. Gaitanis, DEMOKRITOS
12:00 - 13:30 Lunch
13:30 - 14:50
- Session 7: TSC Checkers - 1
Moderator : TBA
7.1 An Efficient Test Generation for Multiple Fault Coverage in Totally Self-Checking Checker, J. Pang, M. Wong, Y.S. Lee, Hong Kong Polytechnic U.
7.2 Transistor-level Implementation of Totally Self-Checking Checkers for a Subset m-out-2m Codes, P. Lala, F. Busaba, M. Zhao, North Carolina A&T State U.
7.3 Modular Design of Self-Testing Checkers for m-out-of-n Codes, S. Piestrak, TU. of Wroclaw
7.4 Embedded 1-out-of 3 Checkers with On-line Testing Ability, C. Metra, M. Favalli, B. Ricco, DEIS-U. of Bologna
15:30 Social Event: TBA
Wednesday, July l0, l996
8:30 - 9:50
- Session 8 : TSC Checkers - 2
Moderator : TBA
8.1 Compact and High Speed Berger Code Checker, C. Metra, J. Lo, DEIS-U. of Bologna
8.2 Design of Totally Self-Checking Checkers for a Class of Hamming Distance Codes, C. Bolchini, F. Salice, D. Sciuto, Politecnico di Milano
8.3 Optimal Self-Testing Embedded Two-Rail Checkers, D. Nikolos, U. of Patras
8.4 A TSC Berger-Code Checker for 2r-l Bit Information, W. Chang, C. Wu, National Tsing Hua U.
9:50 - 10:10 Coffee Break
10:10 - 11:30
- Session 9: On-Line and Off-Line BIST
Moderator : Y. Zorian, Lucent Technologies
9.1 Design of Scalable Hardware Test Generators for On-Line BIST, H. Al-Asaad, J. Hayes, U. of Michigan, B. Murray, General Motors R&D Center
9.2 Formal Verification and Synthesis of On-Line Self-Test A. Hunter, R. Tully, R. Zimmer, I. Dear, T. Ambler, Brunel U.
9.3 Enhancing BIST Transition Fault Coverage by TPG Output Permutation, D. Miller, J.M. Kadri, U. of Victoria
9.4 Multifeedback: A New TPG Architecture for Integrated Test, H. Viallon, C. Dufaza, U. Montpellier II
11:30 - 11:50 Coffee Break
11:50 - 13:10
- Session 10: Diagnosis and Fault Tolerance
Moderator : TBA
10.1 Field Diagnosis and Fault-Tolerance Issues Using O.O. Agents for Mobile Computing, P. Trane, Tokyo Institute of Technology
10.2 Comparison of Self-Diagnosis Algorithms Performances, O. Benkahla, F. Chevassu, B. Remy, C. Robach, IMAG-LSR
10.3 On-Line Fault Resilience Through Gracefully Degradable ASIC's, W. Chan, A. Orailoglu, U. of California
10.4 Quantitative Comparisons of TMR Implementation, D. Audet, N. Gagnon, U. of Quebec, Y. Savaria, Ecole Polytechnique de Montreal
13:10 - 14:30 Lunch
- General Chair
- M. Nicolaidis, TIMA - France
- Program Chairs
- D. Pradhan, Texas A&M U. - USA
- Vice General Chair
- Y. Zorian, Lucent Technologies - USA
- Local Arrangements
- C. Dufaza, LIRMM - France
- R. Leveugle, CSI/INPG - France
- Publications Chair
- M. Chatterjee, Texas A&M U. - USA
- ETTTC Liaison
- C. Landrault, LIRMM - France
J. A. Abraham - U. of Texas
M. Abramovici - Lucent Technologies
L. Alkalai -JPL/Caltech
D. Avresky -Texas A&M U.
E. Boehl - Robert Bosch GmbH
B. Bose - Oregon State U.
S. Bracho - U. of Cantabria
T. Calin - TIMA
K.T. Cheng - UCSB
R. David - LAG
W. Debaney - Rome Lab. RL/ERDA
R. O. Duarte - TIMA
J.P. Hayes - U. Michigan
J. Figueras -U. Polit. de Catalunya
Ph. Forin - Matra Transport
W. K. Fuchs - U. Illinois
M. Giraud - Dassault Electronique
M. Goessel - Max-Plank Society
S. Gupta - USC
B. Kaminska - Ecole Pol. Montreal
N. Kanopoulos -DCT
K. Kuchukian - Armenian NAS
D. Levi - CEP SYSTEMS
P.K. Lala - N. Carolina A&T State U.
J. Y. LeGall - Alcatel Espace
J. C. Lo - Rhode Island U.
J. Marshall - Ioral Federal Systems
P. Marchal - CSEM SA
C. Metra - U. Bologna
E. J. McCluskey - Stanford U.
T. Nanya - Tokyo Inst. of Techn.
D. Nicolos - U. Patras
A. Orailoglu - U. of CA, San Diego
A. Paschalis - NCSR Demokritos
P. Prinetto - Politecnico di Torino
S. M. Reddy - Iowa U.
F. Simon - Alcatel Alsthom Rech.
A. D. Singh - Auburn U.
E. S. Sogomonyan - Rus. A. of Sc.
J. Stiffler - Sequoia Systems
V. Szekely - TU Budapest
R. Velazco - LGI/INPG
T. Williams - IBM
C.W. Wu - Nat. Tsing Hua U.
H. J. Wunderlich - U. Siegen
LOCATION AND SOCIAL EVENT
A block of rooms has been reserved at the Hotel Helianthal, Saint-Jean-de-Luz, Biarritz. Reservations should be made directly and by June 17th. July is a high season for Biarritz and rooms cannot be guaranteed after this date.
WORKSHOP LOCATION: Hotel Helianthal is located beside the beach, in the center of Saint-Jean-de-Luz, on the outskirts of Biarritz. Biarritz is a renowned tourist resort, famous for its history and rich in its landscape. Lying along the Atlantic coast in south-west France, Biarritz offers the pleasures of sea sports under a salubrious climate. It also lies in the close proximity of the enchanting Pyrenees, which extend further south into Spain.
TRAVEL INFORMATION: Well connected by air and rail to the other major cities nearby, Biarritz makes an ideal venue for this conference.
National airport: Biarritz-Anglet-Bayonne airport offers:
- 5 direct flights from and to Paris-Orly, every day,
- 2 direct flights from and to Lyon, Marseille, every day,
- 2 direct flights from and to Nice Montpellier, Gen¶ve, weekly.
Bus: Saint-Jean-de-Luz is located 15mm by bus shuttle of Biarritz-Anglet-Bayonne airport.
Train: 3 direct high speed trains (TGV) arrive and leave directly from and to Paris (5 hours trip),
2 trains from and to Lyon, Nice-Marseille, every day.
Car rentals: In Biarritz, all major car rental companies have offices at the airport or in town, most of them in front of the railway station.
Taxi: The cost of a taxi ride between Biarritz-Anglet-Bayonne airport and Saint-Jean-de-Luz is approximately FF150.
Social Event: To be determined.