ASYNC 2006

12th IEEE International Symposium on Asynchronous Circuits and Systems

March 13-15, 2006, Grenoble, France
Async 2006 PDF Presentations
09:00-09:30 Introduction
Marc Renaudin Introduction
09:30-10:30 Invited Talk 1
Asynchronous Design: An Enabler for Flexible Microelectronics (7064Ko).
11:00-12:30 Session 1: Interfacing and Synchronization
Measuring Deep Metastability (426Ko).
A Level-Crossing Flash Asynchronous Analog-to-Digital Converter (730Ko).
An Asynchronous High-Throughput Control Circuit For Proximity Communication (8954Ko).
14:00-15:30 Session 2: Fault-tolerance and testing
Self-Healing Asynchronous Arrays (230Ko).
Low-Overhead Testing of Delay Faults in High-Speed Asynchronous Pipelines (297Ko).
A Transistor-Level Test Strategy for C2MOS MOUSETRAP Asynchronous Pipelines (325Ko).
16:00-17h30 Session 3: Novel architectures and Design practices
A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations (427Ko).
An ultra-low energy asynchronous processor for Wireless Sensor Networks (2750Ko).
AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation (1171Ko).
09:00-10:00 Invited Talk 2
ATRS: an alternative roadmap for semiconductors, technology evolution and impacts on system architecture (923Ko).
10:30-12:00 Session 4: Interconnect and Communications
Surfing Interconnect (631Ko).
Multiple-rail Phase-encoding for NoC (190Ko).
Fast Asynchronous Shift Register for Bit-Serial Communication (5714Ko).
14:00-15:00 Session 5: Synthesis
Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks (8954Ko).
Synthesising Heterogeneously Encoded Systems (8954Ko).
15:30-18:00 Industrial session
Brees Roger (Boeing) (1366Ko)
Rik Van de Wiel (Handshake Solutions) (1910Ko)
John Willis (FTL) (1210Ko)
• John Bainbridge (Silistix)
Andrew Lines (Fulcrum) (2907Ko)
09:00-10:00 Invited Talk 3
Asynchronous Architectures for Nanometer Scales (834Ko).
10:30-12:00 Session 6: Design and Architectures for GALS
GALS at ETH Zurich: Success or Failure ? (1655Ko).
Interface Design for Rationally Clocked GALS Systems (295Ko).
Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture (1089Ko).
13:30-14:30 Session 7: Slack Matching
Slack Matching Asynchronous Designs (377Ko).
Slack Matching Quasi Delay-Insensitive Circuits (3230Ko).
14:30-15:00 Best Paper Award (774Ko) - Closing Session (52Ko).
©2006 Laboratoire TIMA.
Tous droits réservés.