ASYNC 200612th IEEE International Symposium on Asynchronous Circuits and Systems
March 13-15, 2006, Grenoble, France
Monday Invited talk
By: Nobuo Karaki, Seiko Epson Corp., Japan.
"Asynchronous Design: An Enabler for Flexible Microelectronics"
Flexible microelectronics technology featuring low-temperature poly silicon (LTPS) TFT and surface free technology by laser annealing and ablation (SUFTLAR) is expected to become a platform for developing thin, flexible and low-cost display devices. LTPS TFTs are good for realizing large area displays and integrated circuits at lower cost. A drawback of LTPS TFTs, however, is that they have substantial deviations in characteristics, which are caused by deviations mainly in crystal grain size and thickness of silicon-oxide. Until now, these deviations were considered to be beyond the capability of synchronous circuit design, especially for large-scale circuits such as microprocessors driven by global clocking. Since asynchronous circuits are “self-timed”, they absorb the deviations of device characteristics. Plus they run as faster as possible in event-driven fashion dissipating less power, and remain on standby for quick service. Even with the benefits of asynchronous circuits, it is considered difficult to proceed with circuit design using syntax-directed translation using VLSI programming languages such as CSP, Tangram and OCCAM, syntax of which is far from the standard HDL. The authors then decided to develop Verilog+ that comprises a subset of Verilog HDLR and minimal primitives used for describing the communications between processes. Flexible 8-bit asynchronous microprocessor ACT11 is the first successful instance of asynchronous design using Verilog+ without knowledge of element and wire delay except for datapath.
Manager, Technology Platform Research Center
Seiko Epson Corp.
Tuesday Invited talk
By: Jean-Pierre Schoellkopf, STMicroelectronics, France.
"ATRS: an alternative roadmap for semiconductors, technology evolution and impacts on system architecture"
The recent evolution of semiconductor technology, in the last decades, brought tremendous improvements in performance increase at decreasing prices, perfectly following the famous Moore’s law. Lithography is still improving and allows 0.7X linear shrink per technology node. However, many products are hitting the “power wall”! Silicon is free, but peak power consumption, power density, heat dissipation are preventing a straight usage of the available silicon area. The simple shrink, even if it is a perfect way for cost reduction, does not support power density increase, and is not supported by packaging technology which does not scale as fast as silicon. On the other hand, scaling allows to double transistor count at each node at constant die size: then the challenge for tomorrow consists in improving performance while maintaining a reasonable power consumption. Architects and designers must improve MOPS/Watt. In the old times, VDD was scaled by 0.7, so there was enough room to increase both complexity and clock frequency. This talk will present an “alternative roadmap” which is proposing a way to maintain power consumption stable (from today and forever): increase complexity as much as allowed by lithography, implementing a lot of parallelism at decreased clock frequency, with a moderate VDD scaling. There is a big impact on parallel architectures, memory hierarchy, and a bigger impact on device characteristics. We’ll demonstrate that device performance must be relaxed compared to the ITRS roadmap, allowing to handle the leakage power crisis and to manage the huge problems due to technology variations. Low frequency and/or asynchronous operating modes are seen as mandatory ways for power management.
Central CAD & Design Solutions
Director – Advanced Digital Design
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Wednesday Invited talk
By: Ferdinand Peper, National Institute of Information and Communications Technology, Japan.
"Asynchronous Architectures for Nanometer Scales"
The ongoing developments in nanotechnology promise extremely powerful computers, but they may require new designs. Heat dissipation will become a major issue at the high integration densities allowed by nanotechnology, and it is therefore unsurprising that techniques to reduce it, like asynchronous timing, have attracted growing interest in recent years. At the same time, some researchers have come to realize that the types of signal and circuit realizable by nanotechnology may be very different from those in solid-state electronics. Signals, for example, may be encoded by particles, giving them a token-like nature. Primitive operators in circuits will have to be designed with this in mind, and asynchronous circuits are no exception to this.
Ease of manufacturing is another important issue for nanocomputer designs. A regular structure tends to facilitate bottom-up manufacturing techniques like directed molecular self-assembly. Cellular automata are obvious candidates in this context. Though asynchronous cellular automata have been investigated for years, the methods to compute on them have been limited to simulating synchronous cellular automata on them. As this requires that all cells are busy most of the time with ensuring that they run approximately in lock-step with each other, this method is unlikely to reduce power consumption of the cells in physical implementations, defeating the use of asynchronous timing in the first place. This presentation shows an alternative, in which only cells in the neighbourhood of signals are active while the others are quiescent. This method is based on the embedding of delay-insensitive circuits on asynchronous cellular automata
Senior Research Scientist
National Institute of Information and Communications Technology
Kansai Advanced Research Center
588-2 Iwaoka, Nishi-ku Kobe
Tous droits réservés.