ASYNC 200612th IEEE International Symposium on Asynchronous Circuits and Systems
March 13-15, 2006, Grenoble, France
Call for Papers
The International Symposium on Asynchronous Circuits and Systems provides a high quality forum for scientists and engineers to present their latest research findings. Authors are invited to submit full papers on all aspects of asynchronous design. Topics of interest include, but are not limited to:
• Mixed synchronous/asynchronous architectures, interfaces, and circuits.
• High-speed/low-power asynchronous logic, memories, and interconnects.
• High-level design and synthesis of self-timed circuits.
• Physical design of unclocked logic and pipelines.
• Formal methods for correctness and performance analysis of asynchronous designs.
• Test, reliability, security, and radiation tolerance.
• CAD for asynchronous design and validation.
• Asynchronous System-on-a-chip (SoC).
• Novel asynchronous architectures.
• Asynchrony and latency tolerance in system-level design.
Papers should be submitted via the conference web site.
The submission should not exceed ten pages in IEEE double column format. Papers that exceed the length limit may not be reviewed. Papers will be evaluated by the program committee and reviews will be based on scientific merit, innovation, relevance, and presentation. New-idea papers are encouraged, and the program committee recognizes that such papers may contain less evaluation than papers in established areas. Accepted papers will be published in a proceedings that will be distributed at the conference.
• Submission deadline: 3 October 2005
• Notification of acceptance: 12 December 2005
• Final version due: 5 january 2006
• Paper Format: abstract of up to 150 words, 10 pages or fewer, including figures, single spaced, 10 pts or larger font size and IEEE double column conference format.
Tous droits réservés.