From 2005 to 2014:
    7 International journals
    2 Patents (dépôts APP)
    6 Invited conferences
   65 International conferences
   11 Book chapters
    2 Edited books
    2 National conferences
    6 Other presentations
    1 Open source software
    5 PhD

7 International journals

 1 Morin-Allory K., Boulé M., Borrione D., Zilic Z., Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 29, page: 1436 - 1448 (2010)
 
 2 Borrione D., Helmy A., Pierre L., Schmaltz J., A Formal Approach to the Verification of Networks on Chip, EURASIP Journal on Embedded Systems, Volume 2009, Article ID 548324, page: 14 (2009)
 
 3 Schmaltz J., Borrione D., A functional formalization of on chip communications, Formal Aspects of Computing, Vol.20, page: 241-258 (2008)
 
 4 Pierre L., Ferro L., A Tractable and Fast Method for Monitoring SystemC TLM Specifications , IEEE Transactions on Computers, Vol. 57, page: 1346-1356 (2008)
 
 5 Morin-Allory K., Gascard E., Borrione D., Synthesis of property monitors for online fault detection, Journal of Circuits, Systems, and Computers (JCSC) , 16, page: 943 - 960 (2007)
 
 6 Schmaltz J., Borrione D., A Generic Network on Chip Model, Lecture Notes in Computer Science, , page: 310-325 (2005)
 
 7 Morin-Allory K., Cachera D., Proving Parameterized Systems: the use of pseudo-pipelines in polyhedral logic, Lecture Notes in Computer Science, Volume 3725 , page: 376 (2005)
 
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2 Patents (dépôts APP)

1 Ferro L., Pierre L., Logiciel ISIS, FR.001.500008.000.S.P.2010.000.31500 (14/12/2010)
 
2 Borrione D., Ferro L., Morin-Allory K., Oddos Y., Pierre L., Logiciel HORUS, FR.001.220016.000.S.P.2009.000.31500 (27/05/2009)
 
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6 Invited conferences

1 Pierre L., Assertion-Based Verification for the validation and safety analysis of hardware/software systems on chip, TORRENTS Working day (RTRA Sciences et Technologies pour l'Aéronautique et l'Espace) Toulouse, France (13/12/2013)
 
2 Borrione D., Javaheri N., Morin-Allory K., Porcher A., Automatic Prototyping of declarative properties on FPGA, Electronic System Level Synthesis Conference (ESLsyn 2013), Austin, Texas, USA (02/06/2013)
 
3 Pierre L., Runtime verification of functional requirements for SoC models: integration of PSL in SystemC TLM, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes, Leysin, Suisse (07/01/2013)
 
4 Borrione D., Assertion Based Test, Forum on specification & Design Languages (FDL'08), Stuttgart, Germany, September 23-25 (2008)
 
5 Borrione D., HORUS: proven correct support for on-line property verification, FETCH'08, Ecole d'Hiver Francophone sur les Technologies de Conception des systèmes embarqués Hétérogènes, Montebello, Québec, Canada, January 7-9 (2008)
 
6 Borrione D., Liu Z.W., Morin-Allory K., Ostier P., Fesquet L., On-Line Assertion-Based Verification with Proven Correct Monitors, 3rd IEEE International Conference on Information and Communication Technology (ICICT'05), December 5-6, 2005. cairo, EG (2005)
 
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65 International conferences

  1 Pierre L., Chabot M., Customization of the Runtime Verification of Hardware Software Virtual Platforms in ISIS, Forum on specification & Design Languages (FDL'2014) (14/10/2014) - Démo
 
  2 Bel Hadj Amor Z., Pierre L., Borrione D., A Tool for the Automatic TLM-to-RTL Conversion of Embedded Systems Requirements for a Seamless Verification Flow, International Conference on Very Large Scale Integration (VLSI-SoC'14) (06/10/2014)
 
  3 Chabot M., Pierre L., A Customizable Monitoring Infrastructure for Hardware/Software Embedded Systems, Proc. 26th IFIP International Conference on Testing Software and Systems (ICTSS'2014) (23/09/2014)
 
  4 Bel Hadj Amor Z., Pierre L., Borrione D., System-on-Chip Verification: TLM-to-RTL Assertions Transformation, 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME'14), Grenoble, France (30/06/2014)
 
  5 Morin-Allory K., Javaheri N., Borrione D., Design Understanding with Fast Prototyping from Assertions, Workshop on Design Automation for Understanding Hardware Designs (Friday Workshop DATE'14), Dresden (Germany) (28/03/2014)
 
  6 Borrione D., Fast Prototyping from Assertions, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH 2014), Ottawa, Canada (08/01/2014)
 
  7 Morin-Allory K., Javaheri N., Borrione D., Fast Prototyping from Assertions: a Pragmatic Approach, 11th ACM-IEEE International Conference on "Formal Methods and Models for Codesign (MEMOCODE 2013), Portland , Oregon, USA (18/10/2013)
 
  8 Morin-Allory K., Javaheri N., Borrione D., SyntHorus-2: Automatic Prototyping from PSL, IFIP/IEEE International Conference On Very Large Scale Integration (VLSI-SoC'13), Istanbul (Turkey) (07/10/2013)
 
  9 Pierre L., Bel Hadj Amor Z., Automatic Refinement of Requirements for Verification throughout the SoC Design Flow, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'13), Embedded Syst Week), Montreal (Canada) (29/09/2013)
 
 10 Pierre L., Pancher F., Suescun R., Quévremont J., On the Effectiveness of Assertion-Based Verification in an Industrial Context, 18th International Workshop on Formal Methods for Industrial Critical Systems (FMICS'2013), Madrid (Spain) (23/09/2013)
 
 11 Pierre L., A Formal Framework for Testing with Assertion Checkers in Mixed-Signal Simulation, IEEE International Conference on Electronics, Circuits, and Systems (ICECS'2012), Seville (Spain) (09/12/2012)
 
 12 Paugnat F., Fesquet L., Morin-Allory K., Model of a Simple yet effective Operational Amplifier, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD'12), Seville, Spain (19/09/2012)
 
 13 Pierre L., Ferro L., Bel Hadj Amor Z., Bourgon P., Quévremont J., Integrating PSL Properties into SystemC Transactional Modeling - Application to the Verification of a Modem SoC, IEEE International Symposium on Industrial Embedded Systems (SIES'2012), Karlsruhe (Germany) (02/06/2012)
 
 14 Tsiligiannis G., Pierre L., A Mixed Verification Strategy Tailored for Networks on Chip, Sixth IEEE/ACM International Symposium on Networks on Chip (NoCS'12), Copenhagen, Denmark (09/05/2012)
 
 15 Ouchet F., Morin-Allory K., Fesquet L., C-elements for hardened self-timed circuits, 21st International Workshop Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation (PATMOS'11), Madrid, Spain (26/09/2011)
 
 16 Porcher A., Morin-Allory K., Fesquet L., Does Asynchronous technology bring robustness in synchronous circuit monitoring?, Forum on specification & Design Languages (FDL’11), Oldenburg, Germany (13/09/2011)
 
 17 Pierre L., Damri L., Improvement of Assertion-Based Verification through the Generation of Proper Test Sequences, Forum on specification & Design Languages (FDL'11), Oldenburg, Germany (13/09/2011)
 
 18 Ferro L., Pierre L., Bel Hadj Amor Z., Lachaize J., Lefftz V., Runtime Verification of Typical Requirements for a Space Critical SoC Platform, Proc. 16th International Workshop on Formal Methods for Industrial Critical Systems (FMICS’11), Trento (Italy) (29/08/2011)
 
 19 Clavel R., Pierre L., Leveugle R., Towards Robustness Analysis using PVS, Proc. Conference on Interactive Theorem Proving (ITP’11), Nijmegen, Netherlands (22/08/2011)
 
 20 Porcher A., Morin-Allory K., Fesquet L., Synthesis of Quasi Delay Insensitive Monitors, 7th Conference on PhD Research in Microelectronics and Electronics (PRIME’11), Madonna Di Campiglio (Trento), Italy (03/07/2011)
 
 21 Paugnat F., Bousquet L., Morin-Allory K., Fesquet L., A Performance Comparison Between the SystemC-AMS Models of Computation, edaWorkshop 2011, Dresden, Germany (10/05/2011)
 
 22 Yan C., Ouchet F., Fesquet L., Morin-Allory K., Formal Verification of C-element Circuits, IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC’11), Ithaca (NY) (27/04/2011)
 
 23 Pierre L., Ferro L., Enhancing the assertion-based verification of TLM designs with reentrancy, 8th IEEE/ACM International Conference Formal Methods and Models for Codesign (MEMOCODE'10), Grenoble, France (26/07/2010)
 
 24 Lefftz V., Bertrand J., Cassé H., Clienti C., Coussy P., Maillet-Contoz L., Mercier P., Moreau P., Pierre L., Vaumorin E., A Design Flow for Critical Embedded Systems, Proc. IEEE Symposium on Industrial Embedded Systems (SIES’10), Trento, Italy (07/07/2010)
 
 25 Ouchet F., Morin-Allory K., Fesquet L., Delay Insensitivity Does Not Mean Slope Insensitivity!, IEEE Symposium on Asynchronous Circuits and Systems (ASYNC'10), Grenoble, France (03/05/2010)
 
 26 Porcher A., Morin-Allory K., Fesquet L., Synthesis of asynchronous monitors for critical electronic systems, IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS’10), Vienna, Austria (14/04/2010)
 
 27 Helmy A., Pierre L., Jantsch A., Theorem proving techniques for the formal verification of NoC communications with non-minimal adaptive routing, Symposium on Design and Diagnostics of Electronic Systems (DDECS'10), Vienna (Austria) (14/04/2010)
 
 28 Ferro L., Pierre L., Formal Semantics for PSL Modeling Layer and Application to the Verification of Transactional Models , Design, Automation and Test in Europe (DATE'10), Dresden (Germany) (09/03/2010)
 
 29 Oddos Y., Morin-Allory K., Borrione D., Synthorus: Highly Efficient Automatic Synthesis from PSL to HDL, International Conference On Very Large Scale Integration (VLSI-SoC'09), Florianopolis, Brazil (12/10/2009)
 
 30 Baarir S., Braunstein C., Clavel R., Encrenaz E., Ilié J.-M., Leveugle R., Mounier I., Pierre L., Poitrenaud D., Complementary formal approaches for dependability analysis, International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'09), Chicago, Illinois, USA (07/10/2009)
 
 31 Ferro L., Pierre L., ISIS: Runtime Verification of TLM Platforms, Forum on specification & Design Languages (FDL'09), Sophia-Antipolis (France) (22/09/2009)
 
 32 Alsayeg K., Morin-Allory K., Fesquet L., RAT-based formal verification of QDI asynchronous controllers, Forum on specifications and Design Languages (FDL’09), Sophia Antipolis, France (22/09/2009)
 
 33 Pierre L., Clavel R., Leveugle R., ACL2 for the Verification of Fault-Tolerance Properties: First Results, International Workshop on The ACL2 Theorem Prover and Its Applications (EPTCS'09), Boston, MA., USA (11/05/2009)
 
 34 Oddos Y., Boulé M., Morin-Allory K., Borrione D., Zilic Z., MYGEN: Automata-based On-line Test Generator for Assertion-based Verification, Proc. 19th Great Lakes Symposium on VLSI (GLSVLSI'09), Boston (MA), USA (01/05/2009)
 
 35 Ouchet F., Borrione D., Morin-Allory K., Pierre L., High-level symbolic simulation for automatic model extraction, Proc. IEEE Symposium on Design and Diagnostics of Electronic Systems (DDECS’09), Liberec (Czech Republic) (15/04/2009)
 
 36 Leveugle R., Pierre L., Maistri P., Clavel R., Soft Error Effect and Register Criticality Evaluations: Past, Present and Future, Workshop on Silicon Errors in Logic - System Effects (SELSE’09), Stanford (CA) (24/03/2009)
 
 37 Oddos Y., Morin-Allory K., Borrione D., Assertion-Based Design with Horus, International Conference on Formal Methods and Models for Codesign (MEMOCODE'2008), Anaheim,CA, USA, June 5-7, 2008 (2008)
 
 38 Oddos Y., Morin-Allory K., Borrione D., Assertion-Based Verification and On-line Testing in Horus, Proc. IEEE International Design and Test Workshop (IDT'08), Monastir (Tunisia), December 20-21 (2008)
 
 39 Borrione D., Helmy A., Pierre L., Schmaltz J., Executable Formal Specification and Validation of NoC Communication Infrastructures, Proc. of 21st Symposium on Integrated Circuits and Systems Design (SBCCI’08), Gramado (Brazil), September 1-4 (2008)
 
 40 Helmy A., Pierre L., Formal Verification of the Communications in Networks on Chips, 2ème Colloque du GdR SoC-SiP, Paris, France, June 4-6 (2008)
 
 41 Ferro L., Pierre L., Ledru Y., Du Bousquet L., Generation of Test Programs for the Assertion-Based Verification of TLM Models, Proc. IEEE International Design and Test Workshop (IDT'08), Monastir (Tunisia), December 20-21 (2008)
 
 42 Anghel L., Fesquet L., Morin-Allory K., Initiation à la conception de VLSI numériques, 10èmes journées pédagogiques CNFM, Saint-Malo, France, November 26-28 (2008)
 
 43 Clavel R., Pierre L., Leveugle R., Premiers résultats sur l'utilisation d'ACL2 pour l'évaluation de la conséquence des erreurs logiques, 2ème Colloque du GdR SoC-SiP, Paris, France, June 4-6 (2008)
 
 44 Morin-Allory K., Boulé M., Borrione D., Zilic Z., Proving and Disproving Assertion Rewrite Rules by Automated Theorem Proving, Proc. of IEEE International High Level Design Validation and Test Workshop (HLDVT'2008), Lake Tahoe, Nevada, USA, November 19-21 (2008)
 
 45 Borrione D., Helmy A., Pierre L., Schmaltz J., A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study, ACM/IEEE International Symposium on Networks-on-Chips (NOCS'2007), Princeton (New Jersey), May 7-9 (2007)
 
 46 Morin-Allory K., Fesquet L., Borrione D., Asynchronous online monitoring of logical and temporal assertions, 10th Forum on Specification and Design Languages (FDL'07), Barcelona, Spain, 18-20 September (2007)
 
 47 Oddos Y., Morin-Allory K., Borrione D., Prototyping Generators for On-line Test Vector Generation Based on PSL Properties, Proc. of IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), Krakow, April 11-13 (2007)
 
 48 Borrione D., Helmy A., Pierre L., ACL2-based verification of the communications in the hermes network on chip, Proc. International Workshop on Symbolic Methods and Applications to Circuit Design (SMACD'06), Firenze, Italy, October 12-13 (2006)
 
 49 Morin-Allory K., Fesquet L., Borrione D., Asynchronous Assertion Monitors for multi-Clock Domain System Verification, Proc. 17th IEEE Symposium on Rapid System Prototyping, Chania, Greece, 14-16 June (2006)
 
 50 Morin-Allory K., Fesquet L., Borrione D., Asynchronous on-line monitoring of PSL assertions, Proc. 17th IEEE Symposium on Rapid System Prototyping, Chania, Greece, 14-16 June (2006)
 
 51 Morin-Allory K., Borrione D., Automatic generation of a provable circuit model: from VHDL to PVS, 8ème International Mathematica Symposium (IMS'06), Avignon, France, 21-23 June (2006)
 
 52 Quinton P., Risset T., Morin-Allory K., Cachera D., Designing parallel programs and integrated circuits, 8ème International Mathematica Symposium (IMS'06), Avignon, France, 21-23 June (2006)
 
 53 Schmaltz J., Borrione D., Formalizing on chip communication in a functional style, Trustworthy Software Workshop, Dagstuhl on-line proceedings, Saarbrücken, Germany, May 15-18 (2006)
 
 54 Morin-Allory K., Borrione D., On-line monitoring of properties built on regular expressions, Proc. Forum on Specification and Design Languages (FDL'06), Darmstadt, Germany, September 19-22 (2006)
 
 55 Oddos Y., Morin-Allory K., Borrione D., On-line test vector generation from temporal constraints written in PSL, Proc. 14th IFIP International Conference on Very Larage Scale Integration (VLSI-SoC’06), Nice, France, October 16-18 (2006)
 
 56 Oddos Y., Morin-Allory K., Borrione D., On-line test vector generation from temporal regular expressions, Intensive Workshop on Service Oriented Computing (IWSOC'06), Le Caire, Egypte, December 16-17 (2006)
 
 57 Borrione D., Morin-Allory K., Proven correct monitors from PSL specifications, Proceedings of the conference on Design, automation and test in Europe. Munich, DE (2006)
 
 58 Schmaltz J., Borrione D., Towards a formal theory of communication architecture in the ACL2 logic, Proceedings of the 6th International Workshop on the ACL2 Theorem Prover and its Applications (ACL2'06), Seattle, WA, USA, August 15-16 (2006)
 
 59 Schmaltz J., Borrione D., A Generic Network on Chip Model, Theorem Proving in Higher Order Logics: 18th International Conference, TPHOLs 2005, Proceedings. Lecture Notes in Computer Science, Volume 3603. (2005)
 
 60 Morin-Allory K., Borrione D., A proof of correctness for the construction of property monitors, High-Level Design Validation and Test Workshop, 2005. Tenth IEEE International. Nappa Valley, US (2005)
 
 61 Zimmermann Y., Toma D., Component Reuse in B Using ACL2, 4th International Conference of B and Z Users (ZBÂ’05), Guildford, UK, April 13-15 (2005)
 
 62 Gascard E., From Sequential Extended Regular Expressions to Determinstic Finite Automata, Information and Communications Technology, 2005. Enabling Technologies for the New Knowledge Society: ITI 3rd International Conference on. Cairo, EG (2005)
 
 63 Morin-Allory K., Cachera D., Proving Parameterized Systems: the use of pseudo-pipelines in polyhedral logic, in Correct Hardware Design and Verification Methods: 13th IFIP WG 10.5Advanced Research, Working Conference, CHARME 2005, October 3-6, 2005, Proceedings. Saarbrücken, DE (2005)
 
 64 Borrione D., Liu M., Ostier P., Fesquet L., PSL-based online monitoring of digital systems, Forum on specification and Design Languages (FDL'05), Lausanne, Switzerland, September 27-30 (2005)
 
 65 Al Sammane G., Borrione D., Chevallier R., Verification of behavioral descriptions by combining symbolic simulation and automatic reasoning, Great Lakes Symposium on VLSI archive Proceedings of the 15th ACM Great Lakes symposium on VLSI. Chicago, Illinois, US (2005)
 
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11 Book chapters

 1 Borrione D., Morin-Allory K., Oddos Y., Property-Based Dynamic Verification and Test, Design Technology for Heterogeneous Embedded Systems, Springer , 157-176 (2012)
 
 2 Pierre L., Ferro L., Dynamic Verification of SystemC Transactional Models, Model-Based Testing for Embedded Systems , CRC Press, Chapter 22 (2011)
 
 3 Ferro L., Pierre L., ISIS: Runtime Verification of TLM Platforms, Advances in Design Methods from Modeling Languages for Embedded Systems and SoC's (Selected Contributions from FDL'09), Springer , 213-226 (2010)
 
 4 Borrione D., Helmy A., Pierre L., Schmaltz J., Formal Verification of Communications in Networks-on-Chip, Networks-on-Chips: Theory and Practice, taylor & francis group, 250 p. (2009)
 
 5 Morin-Allory K., Fesquet L., Roustan B., Borrione D., Asynchronous online monitoring of logical and temporal assertions, Embedded Systems Specification and Design Languages, Springer , 278 p (2008)
 
 6 Morin-Allory K., Borrione D., On-line monitoring of properties built on regular expressions sequences, Advances in Design and Specification Languages for Embedded Systems (Selected Contributions from FDL'06), Springer , 197-207 (2007)
 
 7 Borrione D., Liu M., Ostier P., Fesquet L., PSL-based online monitoring of digital systems, in Advances in Design and Specification Languages for SoCs, Springer , 5-22 (2006)
 
 8 Borrione D., Boubekeur M., Mounier L., Renaudin M., Sirianni A., Validation of Asynchronous Circuit Specifications Using IF/CADP, VLSI-SOC: From Systems to Chips, Springer , 85-100 (2006)
 
 9 Pierre L., VHDL, Software Specification Methods - An overview using a case study, International Scientific and Technical Encyclopedia (ISTE), chapter 10 - pp.179-196 (2006)
 
10 Toma D., Borrione D., Al Sammane G., Combining several paradigms for circuit validation and verification, Construction and Analysis of Safe, Secure, and Interoperable Smart Devices. International Workshop, CASSIS 2004.Revised Selected Papers., Springer , 229-49 (2005)
 
11 Toma D., Borrione D., Formal Verification of a SHA-1 Circuit Core Using ACL2, Theorem Proving in Higher Order Logics: 18th International Conference, TPHOLs 2005. , Springer , 326 (2005)
 
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2 Edited books

1 Borrione D., Advances in Design Methods from Modeling Languages for Embedded Systems and SoC's, Springer , 246 p. (2010)
 
2 Borrione D., Paul W., Correct Hardware Design and Verification Methods, Springer , 412 p. (2005)
 
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2 National conferences

1 Fesquet L., Morin-Allory K., Robin R., Contrôle autonome d'un nano-drone par caméra externe, Journées pédagogiques du CNFM (JPCNFM) (19/11/2014)
 
2 Pierre L., Outils de démonstration automatique et preuve de circuits électroniques, Forum Méthodes Formelles "Preuve de modèle, preuve de programme" (Aerospace Valley - Minalogic) Toulouse, France (04/02/2014)
 
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6 Other presentations

 1 Pierre L., A Model for Assertion-Based Verification of TLM Designs, ISRN: TIMA-RR--07/09-01--FR (2007)
 
 2 Schmaltz J., Borrione D., Towards a Formal Theory of On Chip Communications, ISRN: TIMA-RR--06/09-01--FR (2006)
 
 3 Schmaltz J., Borrione D., A Generic Network on Chip Model, ISRN: TIMA-RR--05/03-06--FR (2005)
 
 4 Schmaltz J., Borrione D., Al Sammane G., Design and Formal Verification of Networks On Chip, ISRN: TIMA-RR--05/12-01--FR (2005)
 
 5 Gascard E., From sequential extended regular expressions to deterministic finite automata, ISRN: TIMA-RR--05/07-01--FR (2005)
 
 6 Cachera D., Morin-Allory K., Proving Parameterized Systems: the use of a widening operator and pseudo-pipelines in polyhedral logic, ISRN: TIMA-RR--05/04-01--FR (2005)
 
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1 Open source software

1 Ouchet F., VSYML, LOGICIEL, 2010 (06/04/2010)
 
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5 PhD

1 Bel Hadj Amor Z., Validation of complex systems on a chip, from TLM level to RTL, These de Doctorat (17/12/2014)
 
2 Damri L., Generation of test sequences for accelerating assertions, These de Doctorat (17/12/2012)
 
3 Ferro L., Verification of temporal properties for SystemC TLM specifications, These de Doctorat (11/07/2011)
 
4 Helmy A., Implementation of automatic demonstration techniques for formal verification of NoCs, These de Doctorat (30/04/2010)
 
5 Oddos Y., Semi-Formal Verification and Automatic Synthesis from PSL to VHDL, These de Doctorat (27/11/2009)
 
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