From 2005 to 2014:
   16 International journals
   10 Invited conferences
  104 International conferences
    3 Book chapters
   11 National conferences
    3 Other presentations
   12 PhD and HDR

16 International journals

 1 Dimopoulos M., Gang Yi, Anghel L., Benabdenbi M., Zergainoh N.-E., Nicolaidis M., Fault-Tolerant Adaptive Routing under an Unconstrained Set of Node and Link Failures for Many-Core Systems-on-Chip, Microprocessors and Microsystems, 38, page: 620–635 (01/08/2014)
 
 2 Zhang Z., Refauvelet D., Greiner A., Benabdenbi M., Pecheux F., On-the-Field Test and Configuration Infrastructure for 2-D-Mesh NoCs in Shared-Memory Many-Core Architectures, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22, page: 1364 - 1376 (01/06/2014)
 
 3 Alberto D., Maistri P., Leveugle R., Forecasting the effects of electromagnetic fault injections on embedded cryptosystems, Information Security Journal: A Global Perspective, 22, page: 237-243 (10/04/2013)
 
 4 Bergaoui S., Wecxsteen A., Leveugle R., Detailed analysis of compilation options for robust software-based embedded systems, JETTA - Journal of Electronic Testing: Theory and Application, 29, April, page: 211-222 (01/04/2013)
 
5 Houssany S., Guibbaud N., Bougerol A. , Leveugle R., Santini T., Miller F., Experimental assessment of cache memory soft error rate prediction technique, IEEE Transactions on Nuclear Science, 60, page: 2734-2741 (01/01/2013)
 
6 Pasca V., Anghel L., Benabdenbi M., Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis, JETTA - Journal of Electronic Testing: Theory and Application, 28 , page: Online First™ (03/08/2012)
 
7 Pasca V., Anghel L., Nicolaidis M., Benabdenbi M., CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems , JETTA - Journal of Electronic Testing: Theory and Application, 28, page: 137-150 (01/02/2012)
 
8 Houssany S., Guibbaud N., Bougerol A. , Leveugle R., Miller F., Buard N., Microprocessor Soft Error Rate Prediction Based on Cache Memory Analysis, IEEE Transactions on Nuclear Science, 59, page: 980-987 (01/01/2012)
 
9 Rusu C., Anghel L., Avresky D., Adaptive inter-layer message routing in 3D networks-on-chip, Microprocessors and Microsystems, 35, page: 613-631 (01/10/2011)
 
10 Bougerol A. , Miller F., Guibbaud N., Leveugle R., Carriere T., Buard N., Experimental demonstration of pattern influence on DRAM SEU and SEFI radiation sensitivities, IEEE Transactions on Nuclear Science, 58, part 2, page: 1032-1039 (01/06/2011)
 
11 Canivet G., Maistri P., Leveugle R., Clédière J., Valette F., Renaudin M., Glitch and laser fault attacks onto a secure AES implementation on a SRAM-based FPGA, Journal of Cryptology, 24, page: 247-268 (01/04/2011)
 
12 Bergaoui S., Vanhauwaert P., Leveugle R., A new critical variable analysis in processor-based systems, IEEE Transactions on Nuclear Science, 57, part 1, page: 1992-1999 (01/01/2010)
 
13 Maistri P., Leveugle R., Double-Data-Rate computation as a countermeasure against fault analysis, IEEE Transactions on Computers, Vol. 57, no. 11, November , page: 1528-1539 (01/01/2008)
 
14 Breveglieri L., Koren I., Maistri P., An operation-centered approach to fault detection in symmetric cryptography ciphers, IEEE Transactions on Computers, Vol. 56, page: 635-649 (01/01/2007)
 
15 Maingot V., Ferron J.B., Leveugle R., Pouget V., Douin A., Configuration errors analysis in SRAM-based FPGAs: software tool and practical results , Microelectronics Reliability, Volume 47, Issues 9-11, September-November , page: pp. 1836-1840, (01/01/2007)
 
16 Leveugle R., Early analysis of fault-based attack effects in secure circuits, IEEE Transactions on Computers, Vol.56, page: 1431-1434 (01/01/2007)
 
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10 Invited conferences

 1 Bhasin S., Maistri P., Regazzoni F., Malicious Wave: a Survey on Actively Tampering Using Electromagnetic Glitch, International Symposium on Electromagnetic Compatibility (EMC 2014), Raleigh Convention Center Raleigh, NC, USA (04/08/2014)
 
 2 Vanhauwaert P., Maistri P., Leveugle R., Papadimitriou A., Hély D., Beroulle V., On error models for RTL security evaluations, 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS'14) (06/05/2014)
 
 3 Anghel L., On the Dependability of 3D Interconnects, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'12), Alpes d'Huez, France (09/01/2012)
 
 4 Anghel L., Huard V., Designing cost-effective robust systems by accurate reliability modeling, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’11), Vancouver, Canada (03/10/2011)
 
 5 Maistri P., Countermeasures against fault attacks: The good, the bad, and the ugly , IEEE International On-line Testing Symposium (IOLTS'11), Athens, Greece (13/07/2011)
 
6 Anghel L., Nicolaidis M., Pasca V., On the dependability of 3D interconnects, Keynote in Opening Session at Dependability Issues in Deep-submicron Technologies Workshop (DDT’11), European Test Symposium (ETS), Trondheim, Norvège (27/05/2011)
 
7 Anghel L., Ferron J.B., Leveugle R., Criticality of Configuration Bits in SRAM-based FPGAs: Predictive Analysis and Experimental Results, Workshop on Design for Reliability and Variability (DRVW’11), Dana Point, CA, USA (04/05/2011)
 
8 Leveugle R., Early robustness evaluation of digital integrated systems, 13th Forum for Design Languages (FDL), Southampton, UK (14/09/2010)
 
9 Anghel L., Nicolaidis M., Defects Tolerant Logic Gates for Unreliable Future Nanotechnologies, Special Session of International Work-Conference on Artificial Neural Networks (IWANN’07), San Sebastian, Spain, June (01/01/2007)
 
10 Anghel L., SET and SEU effects at multiple abstraction levels, Single Event Effects Symposium (SEE'06), Long Beach, CA, USA, March (01/01/2006)
 
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104 International conferences

  1 Bollo M., Maistri P., Composite Fields against Side Channel Analysis for the Advanced Encryption Standard, 21st IEEE International Conference on Electronics Circuits and Systems (ICECS'14) (07/12/2014)
 
  2 Chibani K., Bergaoui S., Portolan M., Leveugle R., Criticality evaluation of embedded software running on a pipelined microprocessor and impact of compilation options, IEEE International Conference on Electronics, Circuits and Systems (ICECS) (07/12/2014)
 
  3 Maistri P., Leveugle R., Bossuet L., Aubert A., Fischer V., Robisson B., Moro N., Maurine P., Dutertre J.M., Lisart M., Electromagnetic analysis and fault injection onto secure circuits, 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'14) (05/10/2014)
 
  4 Chibani K., Ben Jrad M., Portolan M., Leveugle R., Fast accurate evaluation of register lifetime and criticality in a pipelined microprocessor, 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'14) (05/10/2014)
 
  5 Leveugle R., Maistri P., Vanhauwaert P., Lu F., Di Natale G., Flottes M.-L., Rouzeyre B., Papadimitriou A., Hély D., Beroulle V., Hubert G., De Castro S., Dutertre J.M., Sarafianos A., Boher N., Lisart M., Damiens J., Candelier P., Tavernier C., Laser-induced fault effects in security-dedicated circuit, 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'14) (05/10/2014)
 
  6 Pontié S., Maistri P., Leveugle R., An Elliptic Curve Crypto-Processor Secured by Randomized Windows, Digital System Design (DSD), 2014 17th Euromicro Conference on (27/08/2014)
 
 7 Pontié S., Maistri P., Design of a secure architecture for scalar multiplication on elliptic curves, 10th Conference on Ph.D Research in Microelectronics and Electronics (PRIME'14) (30/06/2014)
 
 8 Chibani K., Portolan M., Leveugle R., Fast register criticality evaluation in a SPARC microprocessor, 10th Conference on Ph.D Research in Microelectronics and Electronics (PRIME'14) (30/06/2014)
 
 9 Pontié S., Maistri P., Randomized Windows for a Secure Crypto-Processor on Elliptic Curves, 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2014) (18/06/2014)
 
 10 Saliva M., Cacho F., Huard V., Angot D., Durand M., Federspiel X., Parra M., Bravaix A. , Anghel L., Blanc-Benon P., New Insight about Oxide Breakdown Occurrence at Circuit Level, IEEE International Reliability Physics Symposium (IRPS'14) (01/06/2014)
 
 11 Papadimitriou A., Hély D., Beroulle V., Maistri P., Leveugle R., FPGA emulation of laser attacks against secure deep submicron integrated circuits, Second Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'14) (29/05/2014)
 
 12 Alberto D., Maistri P., Leveugle R., Electromagnetic attacks on embedded devices: a model of probe-circuit power coupling, 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS'14) (06/05/2014)
 
 13 Anghel L., Savulimedu Veeravalli V., Alexandrescu D., Steininger A., Schneider-Hornstein K., Costenaro E., Single Event Effects in Muller C-Elements and Asynchronous Circuits Over a Wide Energy Spectrum, The 10th IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE'14) (01/04/2014)
 
 14 Papadimitriou A., Hély D., Beroulle V., Maistri P., Leveugle R., A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks, Design, Automation and Test in Europe Conference (DATE), Dresden, Germany (24/03/2014)
 
 15 Bergaoui S., Vanhauwaert P., Leveugle R., IDSM: an improved disjoint signature monitoring scheme for processor behavioral checking, 15th Latin-American Test Workshop (LATW'14) (12/03/2014)
 
 16 Dimopoulos M., Gang Yi, Benabdenbi M., Anghel L., Efficient Fault-Tolerant Adaptive Routing under an unconstrained Set of Node and Link Failures for Many Cores System On Chip, Workshop on Dependable Multicore and Transactional Memory Systems (DMTM'14), (joint to HIPEAC event) (22/01/2014)
 
 17 Anghel L., New Approaches in Soft Errors Fault Tolerant Design for digital circuits based on Double Sampling Techniques, Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH 2014), Ottawa, Canada (08/01/2014)
 
 18 Ben Dhia A., Rehman Saif-Ur, Blanchardon A., Naviner L., Benabdenbi M., Chotin-Avot R., Mehrez H., Amouri E., Marrakchi Z., A defect-tolerant cluster in a mesh SRAM-based FPGA, International Conference on Field-Programmable Technology (ICFPT'13), Kyoto, Japan (09/12/2013)
 
 19 Ben Jrad M., Leveugle R., Automated design flow for no-cost configuration error detection in SRAM-based FPGAs, International Conference on ReConFigurable Computing and FPGAs (ReConFig' 13), Cancun, Mexico (09/12/2013)
 
 20 Maistri P., Tiran S., Maurine P., Koren I., Leveugle R., Countermeasures against EM analysis for a secured FPGA-based AES implementation, International Conference on ReConFigurable Computing and FPGAs (ReConFig' 13), Cancun, Mexico (09/12/2013)
 
 21 Rehman Saif-Ur, Benabdenbi M., Anghel L., BIST for Logic and Local Interconnect Resources in a Novel Mesh of Cluster FPGA, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), NY, USA (02/10/2013)
 
 22 Leveugle R., Ben Jrad M., On improving at no cost the quality of products built with SRAM-based FPGAs, 5th Asia Symposium on Quality Electronic Design (ASQED 2013), Penang, Malaysia (26/08/2013)
 
 23 Ben Jrad M., Leveugle R., Evaluating a low cost robustness improvement in SRAM-based FPGAs, IEEE International On-Line Testing symposium (IOLTS'13), Chania, Crete, Greece (08/07/2013)
 
 24 Dimopoulos M., Gang Yi, Benabdenbi M., Anghel L., Zergainoh N.-E., Nicolaidis M., Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip , IEEE International On-Line Testing symposium (IOLTS'13), Chania, Crete, Greece (08/07/2013)
 
 25 Alberto D., Maistri P., Leveugle R., Investigation of Electromagnetic Fault Injection Effects on Embedded Cryptosystems, First Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE'13), Avignon, France (30/05/2013)
 
 26 Maistri P., Tiran S., Maurine P., Koren I., Leveugle R., An evaluation of an AES implementation protected against EM analysis, 23rd ACM international conference on Great lakes symposium on VLSI (GLSVLSI'13), Paris, France (02/05/2013)
 
 27 Ben Jrad M., Leveugle R., Comparison of FPGA platforms for emulation-based fault injections using run-time reconfiguration, Conference on Design of Circuits and Integrated Systems (DCIS'12), Avignon, France (28/11/2012)
 
 28 Nicolaidis M., Pasca V., Anghel L., Through-Silicon-Via Built-In Self-Repair for Aggressive 3D Integration, International On-Line Testing Symposium (IOLTS’12), Sitges, Spain (27/06/2012)
 
 29 Pasca V., Rehman Saif-Ur, Anghel L., Benabdenbi M., Efficient link-level error resilience in 3D NoCs , IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS'12) (18/04/2012)
 
 30 Huard V., Pion E., Cacho F., Croain D., Robert V., Delater R., Mergault P., Engels S., Anghel L., Ruiz Amador N., A predictive bottom-up hierarchical approach to digital system reliability , IEEE International Reliability Physics Symposium (IRPS'12), Anaheim, CA, USA (15/04/2012)
 
 31 Frank T., Chappaz C., Arnaud L., Federspiel X., Colella F., Petitprez E., Anghel L., Electromigration degradation mechanism analysis of SnAgCu interconnects for eWLB package , International Reliability Physics Symposium (IRPS'12), Anaheim, CA, USA (15/04/2012)
 
 32 Wecxsteen A., Bergaoui S., Leveugle R., Detailed analysis of compilation options for robust software-based embedded systems, 13th Latin-American Test Workshop (LATW'12), Quito, Ecuador (11/04/2012)
 
 33 Ben Jrad M., Leveugle R., Pattern-based injections in processors implemented on SRAM-based FPGAs, 13th Latin-American Test Workshop (LATW'12), Quito, Ecuador (11/04/2012)
 
 34 Nicolaidis M., Anghel L., Zergainoh N.-E., Zorian Y., Karnik T., Bowman K., Tschanz J., Lu S.-L., Tokunaga C., Raychowdhury A., Khellah M., Kulkarini J., Vivek De, Avresky D., Design for Test and Reliability in Ultimate CMOS, Design, Automation and Test in Europe (DATE'12), Dresden, Germany (12/03/2012)
 
 35 Ferron J.B., Anghel L., Leveugle R., Towards Low-cost Soft Error Mitigation in SRAM-based FPGAs: a Case Study on AT40K, 3rd IEEE Latin American Symposium on Circuits and Systems (LASCAS'12), Playa del Carmen, Mexico (29/02/2012)
 
 36 Ferron J.B., Anghel L., Leveugle R., Analysis of configuration bit criticality in designs implemented with SRAM-based FPGAs, IEEE Symposium on Industrial Electronics & Applications (ISIEA('12), Langkawi, Malaysia (25/09/2011)
 
 37 Maistri P., Masson F., Leveugle R., Implementation of the Advanced Encryption Standard on GPUs with the NVIDIA CUDA framework, IEEE Symposium on Industrial Electronics9-28 (25/09/2011)
 
 38 Ruiz Amador N., Huard V., Pion E., Cacho F., Croain D., Robert V., Engels S., Flatresse P., Anghel L., Bottom-up digital system-level reliability modeling , Custom Integrated Circuits Conference (CICC'11), San Jose, Ca., USA (19/09/2011)
 
 39 Houssany S., Guibbaud N., Bougerol A. , Leveugle R., Miller F., Buard N., Microprocessor soft error rate prediction based on cache memory analysis, 12th European Conference on Radiation and its Effects on Components and Systems (RADECS'11), Sevilla, Spain (19/09/2011)
 
 40 Frank T., Chappaz C., Leduc P., Arnaud L., Moreau S., Thuaire A., Lorut F., Anghel L., Electromigration Behavior of 3D-IC TSV, Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D IC), in conjuction with ITC, Anaheim, USA (18/09/2011)
 
 41 Maistri P., Leveugle R., 10-gigabit throughput and low area for a hardware implementation of the Advanced Encryption Standard, 14th Euromicro/IEEE Conference on Digital System Design (DSD'11), Oulu, Finland (31/08/2011)
 
 42 Clavel R., Pierre L., Leveugle R., Towards Robustness Analysis using PVS, Proc. Conference on Interactive Theorem Proving (ITP’11), Nijmegen, Netherlands (22/08/2011)
 
 43 Leveugle R., Ben Jrad M., Maistri P., Towards Virtual Fault-based Attacks for Security Validation, IARIA Fourth International Conference on Dependability (DEPEND'11), Nice/Saint Laurent du Var, France (21/08/2011)
 
 44 Fradi A., Nicolaidis M., Anghel L., Memory BIST with address programmability , IEEE international On Line Testing Symposium (IOLTS'11), Athenes, Greece (13/07/2011)
 
45 Yu H., Nicolaidis M., Anghel L., Zergainoh N.-E., Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor , 16th IEEE European Test Symposium (ETS'11),Trondheim, Norway (23/05/2011)
 
46 Nicolaidis M., Pasca V., Anghel L., I-BIRAS: Interconnect Built-In Self-Repair and Adaptive Serialization in 3D Integrated Systems , 16th IEEE European Test Symposium (ETS'11), Trondheim, Norway (23/05/2011)
 
47 Zhang Z., Refauvelet D., Greiner A., Benabdenbi M., Pecheux F., Localization of damaged resources in NoC based shared-memory MP2SOC, using a Distributed Cooperative Configuration Infrastructure, 29th IEEE VLSI Test Symposium (VTS’11), Dana Point,California, USA (02/05/2011)
 
48 Frank T., Chappaz C., Leduc P., Arnaud L., Moreau S., Thuaire A., El Farhane R., Lorut F., Anghel L., Resistance Increase Due to Electromigration Induced Depletion Under TSV , IEEE International Reliability Physics Symposium (IRPS’11), Monterey, CA, USA (10/04/2011)
 
49 Pasca V., Anghel L., Benabdenbi M., Configurable Thru-Silicon-Via interconnect Built-In Self-Test and diagnosis , IEEE Latin America Test Symposium Workshop (LATW’11), Porto de Galinhas (PE), Brazil (27/03/2011)
 
50 Bergaoui S., Leveugle R., Impact of software optimization on variable lifetimes in a microprocessor-based system, IEEE International Symposium on Electronic Design, Test and Applications (DELTA'11), Queenstown, New Zealand (17/01/2011)
 
51 Leveugle R., Ben Jrad M., A new methodology for accurate predictive robustness analysis of designs implemented in SRAM-based FPGAs, IEEE International Conference on Electronics, Circuits and Systems (ICECS), Athens, Greece (12/12/2010)
 
52 Frank T., Chappaz C., Leduc P., Arnaud L., Moreau S., Thuaire A., El Farhane R., Anghel L., Reliability approach of high density Through Silicon Via (TSV), 12th Electronics Packaging Technology Conference (EPTC’10), Singapore (08/12/2010)
 
53 Bougerol A. , Miller F., Guibbaud N., Leveugle R., Carriere T., Buard N., Experimental demonstration of pattern influence on DRAM SEU & SEFI radiation sensitivities, European Conference on Radiation and its Effects on Components and Systems (RADECS'10), Längelfeld, Austria (20/09/2010)
 
54 Pasca V., Anghel L., Benabdenbi M., Fault Resilient Intra-die and Inter-die Communication in 3D Integrated Systems, PhD Research in Microelectronics and Electronics Conference (PRIME'10), Berlin, Germany (18/07/2010)
 
55 Canivet G., Maistri P., Leveugle R., Clédière J., Valette F., Renaudin M., Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA, International Conference on Application-specific Systems, Architectures and Processors (ASAP'10), Rennes, France (07/07/2010)
 
56 Nicolaidis M., Pasca V., Anghel L., Interconnect Built-In Self-Repair and Adaptive-Serialization (I-BIRAS) for 3D integrated systems, IEEE International On-Line Testing Symposium (IOLTS’10), Corfu, Greece (05/07/2010)
 
57 Pasca V., Anghel L., Rusu C., Benabdenbi M., Configurable Serial Fault-Tolerant Link for Communication in 3D Integrated Systems, International On-Line Test Symposium (IOLTS'10), Corfu, Greece (03/07/2010)
 
58 Rusu C., Anghel L., Avresky D., RILM: Reconfigurable inter-layer routing mechanism for 3D multi-layer networks-on-chip, International On-Line Test Symposium (IOLTS’10), Corfu, Greece (03/07/2010)
 
59 Pasca V., Anghel L., Benabdenbi M., Fault Tolerant Communication in 3D Integrated Systems, DSN Workshop on Dependable Systems and Networks (WDSN'10), Chicago, USA (28/06/2010)
 
60 Pasca V., Anghel L., Rusu C., Benabdenbi M., Non-regular 3D mesh Networks-on-Chip, DAC Workshop on Diagnostic Services in Network-on-Chips (DSNoC'10), Anaheim, USA (13/06/2010)
 
61 Pasca V., Anghel L., Rusu C., Benabdenbi M., Configurable Fault-Tolerant Link for Inter-die Communication in 3D on-Chip Networks, European Test Symposium (ETS'10), Prague, Czech Republic (24/05/2010)
 
62 Canivet G., Maistri P., Leveugle R., Valette F., Clédière J., Renaudin M., Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA, IEEE European Test Symposium, Prague, Czech Republic (24/05/2010)
 
63 Pasca V., Anghel L., Rusu C., Locatelli R., Coppola M., Error Resilience of Inter-Die and Intra-Die Communication with 3D Spidergon STNoC, Design Automation and Test in Europe Conference, (DATE'10), Dresden, Germany (08/03/2010)
 
64 Rusu C., Anghel L., Checkpoint and rollback recovery in network-on-chip based systems, Asia and South Pacific Design Automation Conference (ASP-DAC’10), Taipei, Taiwan (18/01/2010)
 
65 Bergaoui S., Leveugle R., IDSM: An improved control flow checking approach with disjoint signature monitoring, Conference on Design of Circuits and Integrated Systems (DCIS'09), Zaragoza, Spain (18/11/2009)
 
66 Rusu C., Anghel L., Avresky D., Message routing in 3D networks-on-chip, NORCHIP Conference 2009, Trondheim, Norway (16/11/2009)
 
67 Ferron J.B., Anghel L., Leveugle R., Bocquillon A., Miller F., Mantelet G., A methodology and tool for predictive analysis of configuration bit criticality in SRAM-based FPGAs: experimental results, 3rd International Conference on Signals, Circuits & Systems (SCS'09), Djerba, Tunisia (06/11/2009)
 
68 Maingot V., Leveugle R., Influence of error detecting or correcting codes on the sensitivity to DPA of an AES S-Box, International Conference on Signals, Circuits & Systems (SCS'09), Djerba, Tunisia (06/11/2009)
 
69 Baarir S., Braunstein C., Clavel R., Encrenaz E., Ilié J.-M., Leveugle R., Mounier I., Pierre L., Poitrenaud D., Complementary formal approaches for dependability analysis, International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'09), Chicago, Illinois, USA (07/10/2009)
 
70 Bergaoui S., Vanhauwaert P., Leveugle R., A new critical variable analysis in processor-based systems, European Conference on Radiation Effects on Components and Systems (RADECS'09), Bruges, Belgium (14/09/2009)
 
71 Maistri P., Leveugle R., Toward automated fault pruning with Petri nets, International on-line Testing Symposium (IOLTS’09), Sesimbra-Lisbon, Portugal (24/06/2009)
 
72 Maistri P., Leveugle R., Early pruning of soft errors and transient faults with Petri netS, Electronic Symposium Digest of European Test Symposium (ETS'09), Sevilla, Spain (25/05/2009)
 
73 Di Natale G., Flottes M.-L., Rouzeyre B., Maistri P., Leveugle R., Ensuring High Testability without Degrading Security, European Test Symposium (ETS’09), Seville, Spain (25/05/2009)
 
74 Pierre L., Clavel R., Leveugle R., ACL2 for the Verification of Fault-Tolerance Properties: First Results, International Workshop on The ACL2 Theorem Prover and Its Applications (EPTCS'09), Boston, MA., USA (11/05/2009)
 
75 Canivet G., Leveugle R., Clédière J., Valette F., Renaudin M., Characterization of effective laser spots during attacks in the configuration of a Virtex-II FPGA, IEEE VLSI Test Symposium (VTS'09), Santa Cruz, California, USA (03/05/2009)
 
76 Leveugle R., Calvez A., Maistri P., Vanhauwaert P., Statistical Fault Injection: Quantified Error and Confidence , Design, Automation and Test in Europe (DATE '09), Nice, France (20/04/2009)
 
77 Ferron J.B., Predictive Analysis of Configuration Bit Criticality in SRAM-Based FPGAs. Methodology, tool, and results, RADECS thematic day for Ph.D. students (RADFAC’09), Grenoble, France (09/04/2009)
 
78 Vanhauwaert P., Leveugle R., Efficiency of probabilistic testability analysis for soft error effect analysis: a case study, International conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS’09), Cairo, Egypt (06/04/2009)
 
79 Leveugle R., Calvez A., Vanhauwaert P., Maistri P., Precisely Controlling the Duration of Fault Injection Campaigns: a Statistical View , International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS’09), Cairo, Egypt (06/04/2009)
 
80 Leveugle R., Pierre L., Maistri P., Clavel R., Soft Error Effect and Register Criticality Evaluations: Past, Present and Future, Workshop on Silicon Errors in Logic - System Effects (SELSE’09), Stanford (CA) (24/03/2009)
 
81 Yu H., Nicolaidis M., Anghel L., An Effective Approach to Detect Logic Soft Errors in Digital Circuits Based on GRAAL , International Symposium on Quality of Electronic Design (ISQED’09), San Jose, CA, USA (16/03/2009)
 
82 Maistri P., Pruning Single Event Upset Faults with Petri Nets , Latin-American Test Workshop (LATW’09), Armacao de Buzios, Brazil (02/03/2009)
 
83 Canivet G., Clédière J., Ferron J.B., Valette F., Renaudin M., Leveugle R., Detailed analyses of single laser shot effects in the configuration of a Virtex-II FPGA, 14th IEEE International On-Line Testing symposium, Rhodes, Greece (06/07/2008)
 
84 Maistri P., AES Secured Architecture and Auto-Test Capabilities, PAca Security Trends In embedded Security (PASTIS’08), Gardanne, France (01/01/2008)
 
85 Grecu C., Ivanov A., Saleh S., Rusu C., Anghel L., Pande P.P., Nuca V., A flexible network-on-chip simulator for early design space exploration , 1st Microsystems and Nanoelectronics Research Conference (MNRC 2008), Ottawa, Canada, October 15 (01/01/2008)
 
86 Rusu C., Grecu C., Anghel L., Blocking and Non-blocking Checkpointing for Networks-on-Chip, 2nd IEEE Workshop on Dependable and Secure Nanocomputing (WDSN’08), Anchorage, Alaska, USA, June 27 (01/01/2008)
 
87 Rusu C., Grecu C., Anghel L., Communication Aware Recovery Configurations for Networks-on-Chip, 14th IEEE International Symposium On-Line Testing (IOLT’08), July 7-9 (01/01/2008)
 
88 Rusu C., Grecu C., Anghel L., Coordinated versus Uncoordinated Checkpoint Recovery for Network-on-Chip based Systems, 4th IEEE International Symposium on Electronic Design, Test and Applications (DELTA’08), Hong Kong, January 23-25 (01/01/2008)
 
89 Rusu C., Grecu C., Anghel L., Efficient Coordinated Checkpointing Recovery Schemes for Network-on-Chip based Systems, 2nd International Workshop on Dependable Circuit Design (DECIDE’08), Playa del Carmen, Mexico, November 27-29 (01/01/2008)
 
90 Rusu C., Grecu C., Anghel L., Improving the Scalability of Checkpoint Recovery for Networks-on-Chip, IEEE International Symposium on Circuits and Systems (ISCAS’08), Seattle, Washington, USA, May 18-21 (01/01/2008)
 
91 Canivet G., Clédière J., Valette F., Renaudin M., Leveugle R., Intentional Attacks on SRAM-based FPGAs, 23rd International Conference on Design of Circuits and Integrated Systems (DCIS’08), Grenoble, France, November 12-14 (01/01/2008)
 
92 Clavel R., Pierre L., Leveugle R., Premiers résultats sur l'utilisation d'ACL2 pour l'évaluation de la conséquence des erreurs logiques, 2ème Colloque du GdR SoC-SiP, Paris, France, June 4-6 (01/01/2008)
 
93 Excoffon C., Maistri P., Leveugle R., Software-based BIST capabilities of the Advanced Encryption Standard, Electronic Symposium Digest of 13th IEEE European Test Symposium, Verbania, Italy, May 25-29 (01/01/2008)
 
94 Maistri P., Excoffon C., Leveugle R., Software BIST capabilities of a symmetric cipher, International Conference on Electronics, Circuits and Systems (ICECS), Saint Julians, Malta, September 1-3 (01/01/2008)
 
95 Maistri P., Excoffon C., Leveugle R., Software self-testing of a symmetric cipher with error detection capability, 14th IEEE International On-Line Testing symposium, Rhodes, Greece, July 6-9 (01/01/2008)
 
96 Vanhauwaert P., Portolan M., Leveugle R., Roche P., Usefulness and effectiveness of HW and SW protection mechanisms in a processor-based system, IEEE International Conference on Electronics, Circuits and Systems (ICECS), Saint Julians, Malta, September 1-3 (01/01/2008)
 
97 Rusu C., Bougerol A. , Anghel L., Weulerse C., Buard N., Benhammadi S., Renaud N., Wrobel F. , Carriere T., Multiple Event Transient Induced by Nuclear Reactions in CMOS Logic Cells , IEEE International On-Line Testing symposium (IOLTS’07), Hersonissos-Heraklion, Crete, Greece (08/07/2007)
 
98 Maistri P., Vanhauwaert P., Leveugle R., A novel double-data-rate AES architecture resistant against fault injection, Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC’07), Vienna, Austria, September 10 (01/01/2007)
 
99 Anghel L., Nicolaidis M., Defect Tolerant Logic Gates for Unreliable Future Nanotechnologies, International Conference on Artificial Neural Networks (IWANN), June 20-22, San Sebastian, Spain (01/01/2007)
 
100 Portolan M., Leveugle R., Effective checkpoint and rollback using hardware/OS collaboration, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), Rome, Italy, September 26-28 (01/01/2007)
 
101 Maistri P., Vanhauwaert P., Leveugle R., Evaluation of register-level protection techniques for the Advanced Encryption Standard by multi-level fault injections, International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’07), Rome, Italy, September 26-28 (01/01/2007)
 
102 Bocquillon A., Foucard G., Miller F., Buard N., Leveugle R., Daniel C., Rakers S., Carriere T., Pouget V., Velazco R., Highlights of laser testing capabilities regarding the understanding of SEE in SRAM Based FPGAs, 9th European Conference on Radiation and its Effects on Components and Systems (RADECS’07), Deauville, France, September 10-14, 2007 (01/01/2007)
 
103 Anghel L., Kolonis E., Nicolaidis M., Transient and permanent fault tolerance memory cells for unreliable future nanotechnologies, IEEE Latin American Test Workshop (LATW'05), Salvador Bahia, Brazil (30/03/2005)
 
104 Lazzari C., Anghel L., Reis R., Soft error circuit hardening techniques implementation using an automatic layout generator , Proceedings of IEEE Latin American Test Workshop, Salvador Bahia, Bresil, March 30-April 2 (01/01/2005)
 
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3 Book chapters

1 Anghel L., Nicolaidis M., Cost Reduction and Evaluation of a Temporary Faults Detecting Technique, Design, Automation, and Test in Europe (DATE) “The Most Influential Papers of 10 Years”, Springer , 423-438 (01/01/2007)
 
2 Anghel L., Nicolaidis M., Defects Tolerant Logic Gates for Unreliable Future Nanotechnologies, Computational and Ambient Intelligence , Springer , 422-429 (01/01/2007)
 
3 Anghel L., Rebaudengo M., Sonza Reorda M., Violante M., Multilevel Fault Effects Evaluation, Radiation Effects on Embedded Systems, Springer , 69-88 (01/01/2007)
 
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11 National conferences

1 Chibani K., Portolan M., Leveugle R., Analyse de criticité des registres dans un microprocesseur SPARC, 17èmes Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'14) (26/05/2014)
 
2 Pontié S., Architecture d’un crypto processeur ECC sécurisé contre les attaques physiques, Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'14) (26/05/2014)
 
3 Rehman Saif-Ur, Benabdenbi M., Anghel L., Cost-efficient Testing of LUT and Intra-cluster Interconnect of a Novel SRAM-based FPGA, Colloque National System-On-Chip System-In-Package (SoC-SiP'13) (10/06/2013)
 
4 Ben Jrad M., Leveugle R., Injection de fautes par reconfiguration partielle - Application à un FPGA Virtex II Pro, 13èmes Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'10), Montpellier, France (07/06/2010)
 
5 Bergaoui S., Leveugle R., Nouvelle méthode de vérification de flot de contrôle avec signatures disjointes, 13èmes Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'10), Montpellier, France (07/06/2010)
 
6 Ferron J.B., Anghel L., Leveugle R., Predictive analysis of configuration bit criticality in SRAM-based FPGAs – Methodology, tools, and results, 3ème Colloque du GdR SoC-SiP, Paris, France (10/06/2009)
 
7 Canivet G., Clédière J., Leveugle R., Renaudin M., Valette F., Injection de fautes sur composant Virtex-II XC2V1000 , 11ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’08), Bordeaux, France, Mai 14-16 (01/01/2008)
 
8 Rusu C., Grecu C., Anghel L., Network-on-Chip Fault Tolerance through Checkpoint and Rollback Recovery, National Symposium on System-on-Chip - System-in-Package (GdR SoC-SiP’08), Paris, France, June 4-6 (01/01/2008)
 
9 Dang T., Anghel L., Leveugle R., Structures robustes pour circuits logiques à base de CNTFET, 11ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’08), Bordeaux, France, Mai 14-16 (01/01/2008)
 
10 Vanhauwaert P., Leveugle R., Environnement d’analyse de sûreté sur SoPC, 9èmes Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’06), Rennes, France, May 10-12 (01/01/2006)
 
11 Maingot V., Leveugle R., Redondance d’information : une sécurité suffisante ?, 9ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM’06), Rennes, France, May 10-12 (01/01/2006)
 
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3 Other presentations

1 Yu H., Nicolaidis M., Anghel L., Zergainoh N.-E., Efficient Fault Dectection Architecture Design of Latch-based Low Power DSP/MCU Processor, ISRN: TIMA-RR--2011/01--FR (01/01/2011)
 
2 Maistri P., Pruning Single Event Upset Faults with Petri Nets , ISRN: TIMA-RR--09/03-02-FR (01/01/2009)
 
3 Anghel L., Fesquet L., Morin-Allory K., Initiation à la conception de VLSI numériques, 10èmes journées pédagogiques CNFM, Saint-Malo, France, November 26-28 (01/01/2008)
 
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12 PhD and HDR

 1 Houssany S., Methodology to evaluate microprocessor sensitivity towards cosmic radiations, These de Doctorat (13/09/2013)
 
 2 Ben Jrad M., Robust design of circuits implemented on SRAM-based FPGAs and validation by fault injection, These de Doctorat (01/07/2013)
 
 3 Bergaoui S., Behavioral monitoring for embedded systems and software by disjoint signature analysis, These de Doctorat (06/06/2013)
 
 4 Pasca V., Development of HW / SW Fault-Tolerant and Self-Configurable Architectures for 3D Integration Technologies, These de Doctorat (11/01/2013)
 
5 Ferron J.B., Static analysis of configuration error effects in SRAM-based FPGAs and robustness improvement, These de Doctorat (26/03/2012)
 
6 Ruiz Amador N., Multilevel aging phenomena analysis in complex ultimate CMOS designs, These de Doctorat (01/02/2012)
 
7 Bougerol A. , Failure modes induced by natural radiation environment on DRAM memories: study, test methodology and mitigation technique, These de Doctorat (16/05/2011)
 
8 Canivet G., Analysis of faulted-based attack effects and secure design on a reconfigurable platform, These de Doctorat (23/09/2009)
 
9 Maingot V., Secure Design against fault attacks and side-channel attacks, These de Doctorat (09/06/2009)
 
10 Dang T., CNTFET-based logic gates - characteristic dispersions and defect tolerance, These de Doctorat (25/09/2008)
 
11 Vanhauwaert P., Fault-injection based dependability analysis in a FPGA-based environment, These de Doctorat (04/04/2008)
 
12 Anghel L., CMOS and post CMOS Robust Design, HDR (24/09/2007)
 
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